HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 466

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
Bits 4 to 2—Area 2 and 3 Memory Type (DRAMTP2–DRAMTP0): These bits specify the type
of memory connected to areas 2 and 3. ROM, SRAM, flash ROM, etc., can be connected as
SRAM interface. DRAM and synchronous DRAM can also be connected.
Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description
0
1
Notes: 1. Selection of SRAM interface or MPX interface is determined by the setting of the
Bit 0—Area 5 and 6 Bus Type (A56PCM): Specifies whether areas 5 and 6 are accessed as
PCMCIA interface. The setting of these bits has priority over the MEMMPX bit settings.
Bit 0: A56PCM
0
1
Note:
Rev.7.00 Oct. 10, 2008 Page 380 of 1074
REJ09B0366-0700
2. When this mode is selected, 16 or 32 bits should be specified as the bus width for areas
*
MEMMPX bit
2 and 3. In this mode the MD5 pin is designated for output as the RAS2 pin.
The MD3 pin is designated for output as the CE2A pin.
The MD4 pin is designated for output as the CE2B pin.
0
1
0
1
Description
Areas 5 and 6 are accessed as SRAM interface
Areas 5 and 6 are accessed as PCMCIA interface*
0
1
0
1
0
1
0
1
Areas 2 and 3 are SRAM interface or MPX
interface *
Reserved (Cannot be set)
Area 2 is SRAM interface or MPX
interface *
interface
Areas 2 and 3 are synchronous DRAM
interface
Area 2 is SRAM interface or MPX
interface *
Areas 2 and 3 are DRAM interface *
Reserved (Cannot be set)
Reserved (Cannot be set)
1
1
1
, area 3 is synchronous DRAM
, area 3 is DRAM interface
(Initial value)
(Initial value)
2