HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 667

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 14.9 shows an example of DMA transfer timing in cycle steal mode. The transfer
conditions in this example are dual address mode and DREQ level detection.
Burst Mode: In burst mode, once the DMAC has acquired the bus it holds the bus and transfers
data continuously until the transfer end condition is satisfied. With DREQ low level detection in
external request mode, however, when DREQ is driven high the bus passes to another bus master
after the end of the DMAC transfer request that has already been accepted, even if the transfer end
condition has not been satisfied.
Figure 14.10 shows an example of DMA transfer timing in burst mode. The transfer conditions in
this example are single address mode and DREQ level detection (CHCRn.DS = 0, CHCRn.TM =
1).
Note: Burst mode can be set regardless of the transfer size. A 32-byte block transfer burst mode
Relationship between DMA Transfer Type, Request Mode, and Bus Mode
Table 14.7 shows the relationship between the type of DMA transfer, the request mode, and the
bus mode.
Bus cycle
Bus cycle
DREQ
DREQ
setting can also be made.
CPU
CPU
Figure 14.9 Example of DMA Transfer in Cycle Steal Mode
Figure 14.10 Example of DMA Transfer in Burst Mode
CPU
CPU
CPU
CPU
DMAC
DMAC
Read
Section 14 Direct Memory Access Controller (DMAC)
DMAC
DMAC
Write
Bus returned to CPU
DMAC
Rev.7.00 Oct. 10, 2008 Page 581 of 1074
CPU
DMAC
DMAC
Read
DMAC
DMAC
Write
REJ09B0366-0700
DMAC
CPU
CPU
CPU