HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 286
HD6417750RF240DV
Manufacturer Part Number
HD6417750RF240DV
Description
MPU 3V 16K I-TEMP,PB-FREE 208-QF
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417750RBP240DV.pdf
(1164 pages)
Specifications of HD6417750RF240DV
Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Section 6 Floating-Point Unit (FPU)
Example: If the double-precision FSUB instruction (FSUB DR0, DR2) is executed with input
data DR0 = H'C1F00000 80000000, DR2 = H'C4B250D2 0CC1FB74, and FPSCR = H'000C0001,
the correct operation result is DR2 = H'C4B250D2 0CC1F973, and FPSCR.Flag.I and
FPSCR.Cause.I should be set to 1. However, the result actually produced by the FPU is DR2 =
H'C4B250D2 0CC1F974, and FPSCR.Flag.I and FPSCR.Cause.I are not set to 1.
Effects: In addition to the problem described above, the numerical size of the result of the
operation may contain a minute operation error equivalent to 1/256 of the LSB of the mantissa of
the unrounded value. This is can be described as within the scope of the subsequent rounding
mechanism. Strictly speaking, it consists of the following.
a: The infinite-precision operation result
b: The closest expressible value less than a
c: The closest expressible value greater than a
d: The operation result when a is rounded correctly
e: The operation result when a is rounded by the FPU
• The rounding error when rounding is performed correctly in Round to Nearest mode is:
• The rounding error when rounding is performed correctly in Round to Zero mode is:
6.7.5
The operation result may be incorrect when denormalized numbers are used as input with a
double-precision FDIV, FADD, FSUB, or FMUL instruction, even in the mode capable of
handling denormalized numbers.
Rev.7.00 Oct. 10, 2008 Page 200 of 1074
REJ09B0366-0700
0 ≤ | d − a | ≤ (1/2) × (c − b)
And the rounding error when rounding is performed by the FPU is:
0 ≤ | e − a | < (129/256) × (c − b)
If c – b is considered the LSB of the mantissa, the range of rounding error is equivalent to
1/256 of the LSB of the mantissa of the correctly rounded value.
(
And the rounding error when rounding is performed by the FPU is:
(
If c – b is considered the LSB of the mantissa, the range of rounding error is equivalent to
1/256 of the LSB of the mantissa of the correctly rounded value.
−
−
1) × (c
1) × (c
Notes on FPU Double-Precision Operation Instructions (SH7750 Only)
−
−
b) <
b) <
| d |−| a | ≤
| e |−| a | <
(1/256) × (c − b)
0
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