HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 554

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
Table 13.16 Example of Correspondence between this LSI and Synchronous DRAM
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Burst Read: The timing chart for a burst read is shown in figure 13.28. In the following example
it is assumed that four 512K × 16-bit × 2-bank synchronous DRAMs are connected, and a 64-bit
data width is used. The burst length is 4. Following the Tr cycle in which ACTV command output
is performed, a READA command is issued in the Tc1 cycle, and the read data is accepted on the
rising edge of the external command clock (CKIO) from cycle Td1 to cycle Td4. The Tpc cycle is
used to wait for completion of auto-precharge based on the READA command inside the
synchronous DRAM; no new access command can be issued to the same bank during this cycle. In
this LSI, the number of Tpc cycles is determined by the specification of bits TPC2–TPC0 in MCR,
and commands are not issued for synchronous DRAM during this interval.
The example in figure 13.28 shows the basic cycle. To connect slower synchronous DRAM, the
cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV
command output cycle, Tr, to the READA command output cycle, Tc1, can be specified by bits
RCD1 and RCD0 in MCR, with a value of 0 to 3 specifying 2 to 4 cycles, respectively. In the case
of 2 or more cycles, a Trw cycle, in which an NOP command is issued for the synchronous
DRAM, is inserted between the Tr cycle and the Tc cycle. The number of cycles from READA
Rev.7.00 Oct. 10, 2008 Page 468 of 1074
REJ09B0366-0700
Address Pins (64-Bit Bus Width, AMX2–AMX0 = 011, AMXEXT = 0)
LSI Address Pin
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
—
—
—
RAS Cycle
A22
H/L
0
0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CAS Cycle
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Not used
Not used
Not used
Synchronous DRAM Address Pin
BANK select bank address
Address precharge setting
Function