HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 854

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Serial Communication Interface with FIFO (SCIF)
Figure 16.11 shows an example of the operation for reception in asynchronous mode.
5. When modem control is enabled, the RTS2 signal is output when SCFRDR2 is empty. When
Rev.7.00 Oct. 10, 2008 Page 768 of 1074
REJ09B0366-0700
Serial
data
RDF
FER
RTS2 is 0, reception is possible.
SH7750:
SH7750S, SH7750R: When RTS2 is 1, this indicates that SCFRDR2 contains a number of
1
Start
bit
0
D0
One frame
Figure 16.11 Example of SCIF Receive Operation
D1
(Example with 8-Bit Data, Parity, One Stop Bit)
When RTS2 is 1, this indicates that SCFRDR2 contains 15 or more
bytes of data.
data bytes equal to or greater than the RTS2 output active trigger set
number. The RTS2 output active trigger value is specified by bits 10 to
8 in the FIFO control register (SCFCR2), described in section 16.2.9,
FIFO control register (SCFCR2).
RTS2 also becomes 1 when bit 4 (RE) in SCSCR2 is 0.
Data
D7
RXI interrupt
request
Parity
bit
0/1
Stop
bit
1
Start
bit
0
Data read and RDF flag
read as 1 then cleared to
0 by RXI interrupt handler
D0
D1
Data
D7
Parity
bit
0/1
Stop
bit
ERI interrupt request
generated by receive
error
0
0/1