HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 728
HD6417750RF240DV
Manufacturer Part Number
HD6417750RF240DV
Description
MPU 3V 16K I-TEMP,PB-FREE 208-QF
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417750RBP240DV.pdf
(1164 pages)
Specifications of HD6417750RF240DV
Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Section 14 Direct Memory Access Controller (DMAC)
DMA channel control registers 0−7(CHCR0−CHCR7) are 32-bit readable/writable registers that
specify the operating mode, transfer method, etc., for each channel. Bits 31−28 and 27−24
correspond to the source address and destination address, respectively; these settings are only valid
when the transfer involves the CS5 or CS6 space and the relevant space has been specified as a
PCMCIA-interface space. In other cases, these bits should be cleared to 0. For more information
about the PCMCIA interface, see section 13.3.7, PCMCIA Interface, in section 13, Bus State
Controller (BSC).
No function is assigned to bits 18 and 16 of the CHCR2–CHCR7 registers. Writing to these bits of
the CHCR2–CHCR7 registers is invalid. If, however, a value is written to these bits, it should
always be 0. These bits are always read as 0.
These registers are initialized to H'00000000 by a power-on or manual reset. Their values are
retained in standby, sleep, and deep-sleep modes.
Bits 31 to 29—Source Address Space Attribute Specification (SSA2–SSA0): These bits specify
the space attribute for PCMCIA access. These bits are only valid in the case of page mapping to
PCMCIA connected to areas 5 and 6. For details of the settings, see the description of the SSA2-
SSA0 bits in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3).
Bit 28—Source Address Wait Control Select (STC): Specifies CS5 or CS6 space wait control
for PCMCIA access. This bit selects the wait control register in the BSC that performs area 5 and
6 wait cycle control. For details of the settings, see the description of the STC bit in section 14.2.4,
DMA Channel Control Registers 0−3 (CHCR0−CHCR3).
Bits 27 to 25—Destination Address Space Attribute Specification (DSA2–DSA0): These bits
specify the space attribute for PCMCIA access. These bits are only valid in the case of page
mapping to PCMCIA connected to areas 5 and 6. For details of the settings, see the description of
the DSA2−DSA0 bits in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3).
Bit 24—Destination Address Wait Control Select (DTC): Specifies CS5 or CS6 space wait
cycle control for PCMCIA access. This bit selects the wait control register in the BSC that
performs area 5 and 6 wait cycle control. For details of the settings, see the description of the DTC
bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3).
Bits 23 to 20—Reserved: These bits are always read as 0, and should only be written with 0.
Rev.7.00 Oct. 10, 2008 Page 642 of 1074
REJ09B0366-0700
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