HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 489

MPU 3V 16K I-TEMP,PB-FREE 208-QF

HD6417750RF240DV

Manufacturer Part Number
HD6417750RF240DV
Description
MPU 3V 16K I-TEMP,PB-FREE 208-QF
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF240DV

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF240DV
Manufacturer:
HITACHI
Quantity:
7 287
Bits 26 to 24, 22, and 18—Reserved: These bits are always read as 0, and should only be written
with 0.
Bit 23—CAS Negation Period (TCAS): This bit is valid only when DRAM interface is set.
Bit 23: TCAS
0
1
Bits 21 to 19—RAS Precharge Period (TPC2–TPC0): When the DRAM interface is selected,
these bits specify the minimum number of cycles until RAS is asserted again after being negated.
When the synchronous DRAM interface is selected, these bits specify the minimum number of
cycles until the next bank active command after precharging.
Note: For setting values and the period during which no command is issued, see 22.3.3, Bus
Bit 21: TPC2
0
1
Note:
Timing.
*
Inhibited in RAS down mode.
Bit 20: TPC1
0
1
0
1
CAS Negation Period
1
2
0
1
0
1
0
1
0
1
Bit 19: TPC0
Rev.7.00 Oct. 10, 2008 Page 403 of 1074
Section 13 Bus State Controller (BSC)
DRAM
0
1
2
3
4
5
6
7
RAS Precharge Interval
Synchronous DRAM
1* (Initial value)
2
3
4*
5*
6*
7*
8*
REJ09B0366-0700
(Initial value)

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