MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 105
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number:
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Manufacturer:
Freescale Semiconductor
Quantity:
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State 0—The QUICC asserts RMC in S0 to identify a read-modify-write cycle. The QUICC
places a valid address on A31–A0 and valid function codes on FC3–FC0. The function
codes select the address space for the operation. SIZ1 and SIZ0 become valid in S0 to indi-
cate the operand size. The QUICC drives R/W high for the read cycle.
State 1—One-half clock later in S1, the QUICC asserts AS, indicating a valid address on the
address bus. The QUICC also asserts OE and DS during S1.
State 2—The selected device uses OE, R/W, SIZ1, SIZ0, A0, and DS to place information
on the data bus. Any of the bytes (D31–D24, D23–D16, D15–D8, and D7–D0) are selected
by SIZ1, SIZ0, A1, and A0. Concurrently, the selected device may assert DSACKx.
State 3—As long as at least one of the DSACKx signals is recognized by the end of S2
(meeting the asynchronous input setup time requirement), data is latched on the next falling
edge of the clock, and the cycle terminates. If DSACKx is not recognized by the start of S3,
the QUICC inserts wait states instead of proceeding to S4 and S5. To ensure that wait states
are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchro-
SIZ1–SIZ0
FC3–FC0
DSACKx
D31–D0
A31–A0
CLK
NOTE: OE and WE3–WE0 are not shown.
RMC
R/W
O1
DS
AS
Figure 4-21. Read-Modify-Write Cycle Timing
Freescale Semiconductor, Inc.
S0
For More Information On This Product,
S2
READ
MC68360 USER’S MANUAL
Go to: www.freescale.com
S4
INDIVISIBLE
CYCLE
S0
S2
WRITE
S4
S0
Bus Operation
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