MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 536
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer:
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Quantity:
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Serial Communication Controllers (SCCs)
generates a maskable interrupt, and starts to receive data into the next buffer after one of
the following events:
E—Empty
Bits 14, 8, 6, 5—Reserved
W—Wrap (Final BD in Table)
I—Interrupt
L—Last in Frame
7-212
1. Receiving a user-defined control character
2. Detecting an error
3. Detecting a full receive buffer
4. Issuing the ENTER HUNT MODE command
5. Issuing the CLOSE Rx BD command
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
NOTE: Entries in boldface must be initialized by the user.
0 = The data buffer associated with this Rx BD has been filled with received data, or
1 = The data buffer associated with this Rx BD is empty, or reception is currently in
0 = This is not the last BD in the Rx BD table.
1 = This is the last BD in the Rx BD table. After this buffer has been used, the CP will
0 = No interrupt is generated after this buffer has been used.
1 = The RX bit in the BISYNC event register will be set when this buffer has been
This bit is set by the transparent controller when this buffer is the last in a frame. This
212
data reception has been aborted due to an error condition. The CPU32+ core is
free to examine or write to any fields of this Rx BD. The CP will not use this BD
again while the E-bit remains zero.
progress. This Rx BD and its associated receive buffer are owned by the CP. Once
the E-bit is set, the CPU32+ core should not write any fields of this Rx BD.
receive incoming data into the first BD in the table (the BD pointed to by RBASE).
The number of Rx BDs in this table is programmable and is determined only by the
W-bit and the overall space constraints of the dual-port RAM.
closed by the BISYNC controller. The RX bit can cause an interrupt if it is enabled.
implies the negation of CD in envelope mode or the reception of an error, in which
15
E
14
—
13
W
Freescale Semiconductor, Inc.
For More Information On This Product,
12
I
11
L
MC68360 USER’S MANUAL
Go to: www.freescale.com
10
F
CM
RX DATA BUFFER POINTER
9
DATA LENGTH
—
8
DE
7
—
6
—
5
NO
4
—
3
CR
2
OV
1
CD
0
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