MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 300
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Exar
Quantity:
160
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC68360VR25VLR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 300 of 962
- Download datasheet (4Mb)
Freescale Semiconductor, Inc.
System Integration Module (SIM60)
6.11 GENERAL-PURPOSE CHIP-SELECT OVERVIEW (SRAM BANKS)
Any memory bank that is not used to control DRAM may be used as a general-purpose chip
select, including pins CS0–CS7. This bank is called an SRAM bank. These pins may be
used to support external memory such as SRAM, EPROM, flash EPROM, EEPROM, and
peripherals.
The SRAM banks also have some unique features not available in the DRAM banks. First,
upon system reset, a global (boot) chip select is available. This provides a boot ROM chip
select before the system is fully configured. Second, the SRAM banks offer two-clock
accesses to external SRAM. Finally, each SRAM bank supports a choice of the port size of
its memory or peripheral to be 8, 16, or 32 bits with proper DSACK generation for those port
sizes. Thus, an 8-bit EPROM may be used with a 32-bit SRAM, etc.
6.11.1 Associated Registers
The general-purpose chip selects are controlled by the global memory register (GMR) and
the memory controller status register (MSTAT). There is one GMR and MSTAT in the mem-
ory controller. Additionally, each SRAM bank has a base register (BR) and an option register
(OR).
The GMR is used to control global parameters for both SRAM and DRAM banks.
The MSTAT reports write protect violations and parity errors for both SRAM and DRAM
banks.
The BR and the OR for each of the general-purpose chip selects program most of the fea-
tures. The BR contains a valid (V) bit to indicate that the register information for that chip
select is valid.
6.11.2 8-, 16-, and 32-Bit Port Size Configuration
The general-purpose chip selects support dynamic bus sizing. Defined 8-bit ports are acces-
sible on both odd and even addresses when connected to data bus bits 31–24; defined 16-
bit ports can be accessed as odd bytes, even bytes, or even words when connected to data
bus bits 31–16; and defined 32-bit ports can be accessed as odd bytes, even bytes, odd
words, and even words or long words on long-word boundaries. The port size is specified
by the SPS bits in the OR.
6.11.3 Write Protect Configuration
The WP bit in each BR can restrict write access to its range of addresses. Any attempt to
write this area will result in the WPER bit being set in the MSTAT.
6.11.4 Programmable Wait State Configuration
The general-purpose chip selects support internal DSACKx generation. They allow fast two-
clock accesses to external memory by an internal bus master; from zero-wait-state
accesses (3 clocks) up to 14-wait-state accesses (17 clocks) are allowed for internal bus
masters. For external bus masters, two-clock accesses are not allowed, but 14 wait states
may be programmed. Additionally, if the EMWS bit is set in the GMR, the chip selects can
6-56
MC68360 USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com
Related parts for MC68360VR25VL
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
MC68360 MC68360 Multiple Ethernet Channels on the QUICC
Manufacturer:
Motorola / Freescale Semiconductor
Part Number:
Description:
MC68360 Implementing an 8 bit Eprom for an MC68EC040-MC68360 System
Manufacturer:
Motorola / Freescale Semiconductor
Part Number:
Description:
MC68360 Interfacing the MC68060 to the MC68360
Manufacturer:
Motorola / Freescale Semiconductor
Part Number:
Description:
MC68360 MC68360 RAM Microcode Package Option Overview
Manufacturer:
Motorola / Freescale Semiconductor
Part Number:
Description:
MC68360 MC68360 CPM-CPU Interaction
Manufacturer:
Motorola / Freescale Semiconductor
Part Number:
Description:
MC68360 Interfacing SDRAM to the MC68360 QUICC Device
Manufacturer:
Motorola / Freescale Semiconductor
Part Number:
Description:
MC68360 Interfacing the QUICC to a MCM516400 (4Mx4 10-12 column-row) DRAM
Manufacturer:
Motorola / Freescale Semiconductor
Part Number:
Description:
MC68360 Interfacing the 68360 (QUICC) to T1-E1 Systems
Manufacturer:
Motorola / Freescale Semiconductor
Part Number:
Description:
MC68360 Multiple QUICC Design Concept
Manufacturer:
Motorola / Freescale Semiconductor
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet: