MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 421
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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Figure 7-34 shows the GCI bus signals.
In addition to the 144-kbps ISDN 2B+D channels, the GCI provides five channels for main-
tenance and control functions:
The M channel is used to transfer data between layer 1 devices and the control unit (i.e., the
CPU32+ core). The C/I channel is used to control activation/deactivation procedures or to
switch test loops by the control unit. The M and C/I channels of the GCI bus should be routed
to SMC1 or SMC2, which have modes to support the M and C/I channel protocols.
The QUICC can support any channel of the GCI bus in the primary rate by modifying the SI
RAM programming.
The GCI supports the CCITT I.460 recommendation as a method for data rate adaptation,
since it can access each bit of the GCI separately. The current-route RAM specifies which
bits are supported by the interface and by which serial controller. The receiver will receive
only the bits that are enabled by the SI RAM. The transmitter will transmit only the bits that
L1SYNC
L1RXD
L1TXD
NOTE: L1CLKOx is not shown.
• B1—64 kbps bearer channel
• B2—64 kbps bearer channel
• M—64 kbps monitor (M) channel
• D—16 kbps signaling channel
• C/I—48 kbps C/I channel (includes A and E bits)
L1CLK
is used, (DSCx bit is set in the SIMODE), this output is the L1RCLKx
divided by 2; otherwise, it is simply a 1 output of the L1RCLKx signal.
Note that on the MC68302 this signal was known as GCIDCL.
(2x THE DATA RATE)
x = a and b for TDMa and TDMb.
B1
B1
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 7-34. GCI Bus Signals
MC68360 USER’S MANUAL
Go to: www.freescale.com
B2
B2
NOTE
Serial Interface with Time Slot Assigner
MONITOR
MONITOR
D1 D2
D1 D2
(CLOCK NOT TO SCALE)
C/I
C/I
A E
A E
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