MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 139
![IC MPU QUICC 25MHZ 357-PBGA](/photos/6/76/67680/mfg_mpc860_series_sml.jpg)
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Quantity
Price
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MC68360VR25VL
Manufacturer:
Exar
Quantity:
160
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Part Number:
MC68360VR25VLR2
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4.7 RESET OPERATION
The QUICC has reset control logic to determine the cause of reset, synchronize it if neces-
sary, and assert the appropriate reset lines. The reset control logic can independently drive
five different internal lines:
Table 4-9 summarizes the result of each reset source. Synchronous reset sources are not
asserted until the end of the current bus cycle, regardless of whether RMC is asserted. The
internal bus monitor is automatically enabled for synchronous resets; therefore, if the current
bus cycle does not terminate normally, the bus monitor terminates it. Only single-byte or
word transfers are guaranteed valid for synchronous resets. Asynchronous reset sources
indicate a catastrophic failure, and the reset controller logic immediately resets the system.
Resetting the QUICC causes any bus cycle in progress to terminate as if DSACKx or BERR
had been asserted. In addition, the QUICC appropriately initializes registers for a reset
exception.
1. EXTSYSRST (external system reset) drives the external hard and soft reset pins (RE-
2. EXTRST (external reset) drives the external soft reset pin (RESETS).
3. CLKRST (clock reset) resets the clock module.
4. INTSYSRST (internal system reset) resets the memory controller, system protection
5. INTRST (internal reset) goes to all other internal circuits.
SETH and RESETS).
logic, serial interface, interrupt controller, and parallel I/O modules.
SIZ1–SIZ0
Figure 4-45. Show Cycle Timing Diagram
FC3–FC0
Freescale Semiconductor, Inc.
D31–D0
A31–A0
CLKO1
AS, CS
BKPT
For More Information On This Product,
R/W
DS
S0
MC68360 USER’S MANUAL
Go to: www.freescale.com
SHOW CYCLE
S41
S42
S43
S0
EXTERNAL CYCLE
START OF
S1
S2
Bus Operation
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