MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 173
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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The first column is the value passed to the subroutine, the second column is the value
expected by the table instruction, and the third column is the result returned by the subrou-
tine.
The following value has been calculated for independent variable X:
Since X is an 8-bit value, the upper four bits are used as a table offset, and the lower four
bits are used as an interpolation fraction. The following results are obtained from the sub-
routine:
Thus, Y is calculated as follows:
Y = 80
If the 8-bit value for X were used directly by the table instruction, interpolation would be in-
correctly performed between entries 0 and 1. Data must be shifted to the left four places be-
fore use:
LSL.W #4, Dx
31
Table Entry Offset
Interpolation Fraction
(13 (64 – 80)) / 16 = 67
NOT USED
Table 5-15. T8-Bit Independent Variable Entries
Freescale Semiconductor, Inc.
Dx [4:7] = $B = 11
For More Information On This Product,
(Subroutine)
Dx [0:3] = $D = 13
10
11
12
13
14
15
16
X
0
1
2
3
4
5
6
7
8
9
MC68360 USER’S MANUAL
Go to: www.freescale.com
(Instruction)
16
1024
1280
1536
1792
2048
2304
2560
2816
3072
3328
3584
3840
4096
256
512
768
X
0
15
0
0
0
0
112
128
112
0
16
32
48
64
80
96
96
80
64
48
32
16
Y
0
0
0
0
0
1
0
1
1
1
1
CPU32+
0
0
1
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