MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 156
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Exar
Quantity:
160
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC68360VR25VLR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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CPU32+
5-14
ANDI to CCR
ANDI to SR
ASL,ASR
Opcode
CMPM
ADDQ
BCHG
BGND
CMPA
ABCD
ADDA
ADDX
BCLR
BKPT
BSET
BTST
CHK2
ADDI
ANDI
CMPI
ADD
AND
CMP
BRA
BSR
CHK
CLR
Bcc
Source 10 + Destination 10 + X
Source + Destination
Source + Destination
Immediate Data + Destination
Immediate Data + Destination
Source + Destination + X
Source
Immediate Data
Source
If supervisor state
else TRAP
Destination Shifted by count
If (condition true) then PC + d
~( number of Destination)
~( number of Destination)
~( number of Destination)
0
If (background mode enabled) then
else Format/Vector offset
Run breakpoint acknowledge cycle;
TRAP as illegal instruction
PC + d
~( number of Destination)
1
SP – 4
– ( number of Destination)
If Dn < 0 or Dn > Source then TRAP
If Rn < lower bound or
then TRAP
0
Destination Source
Destination — Source
Destination — Immediate Data
Destination — Source
Destination
enter background mode
PC
SR
(Vector)
If Rn > upper bound
the Source
Destination
bit number of Destination
bit number of Destination
–(SSP)
–(SSP)
Destination
CCR
SP; PC
PC
Freescale Semiconductor, Inc.
PC
Table 5-2. Instruction Set Summary
For More Information On This Product,
SR
CCR
Destination
Operation
SR
(SP); PC + d
MC68360 USER’S MANUAL
cc
Go to: www.freescale.com
Destination
Destination
Destination
cc
–(SSP)
Destination
Z;
Z;
Z;
Z;
bit number of
Destination
PC
Destination
Destination
Destination
Destination
PC
ABCD Dy,Dx
ABCD –(Ay),–(Ax)
ADD ea ,Dn
ADD Dn, ea
ADDA ea ,An
ADDI # data ea
ADDQ # data ea
ADDX Dy,Dx
ADDX –(Ay),–(Ax)
AND ea Dn
AND Dn, ea
ANDI # data ea
ANDI # data ,CCR
ANDI # data ,SR
ASd Dx,Dy
ASd # data ,Dy
ASd ea
Bcc label
BCHG Dn, ea
BCHG #data ea
BCLR Dn, ea
BCLR # data ea
BGND
BKPT # data
BRA label
BSET Dn, eaÒ
BSET # data ea
BSR label
BTST Dn, ea
BTST # data ea
CHK ea ,Dn
CHK2 ea ,Rn
CLR ea
CMP ea ,Dn
CMPA ea ,An
CMPI # data ea
CMPM (Ay)+,(Ax)+
Syntax
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