MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 589
![IC MPU QUICC 25MHZ 357-PBGA](/photos/6/76/67680/mfg_mpc860_series_sml.jpg)
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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MC68360VR25VL
Manufacturer:
Exar
Quantity:
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Company:
Part Number:
MC68360VR25VL
Manufacturer:
Freescale Semiconductor
Quantity:
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7.10.23.21 ETHERNET MASK REGISTER (SCCM). The SCCM is referred to as the Ether-
net mask register when the SCC is operating as an Ethernet controller. It is a 16-bit read-
write register that has the same bit formats as the Ethernet event register. If a bit in the
Ethernet mask register is a one, the corresponding interrupt in the event register will be
enabled. If the bit is zero, the corresponding interrupt in the event register will be masked.
This register is cleared upon reset.
7.10.23.22 ETHERNET STATUS REGISTER (SCCS). This register is not valid for the
Ethernet protocol. The current state of the RENA and CLSN signals may be read in port C.
HDLC SCCE
ETHERNET SCCE
NOTES:
LEGEND:
TENA
CLSN
NOTES:
EVENTS
RENA
TXD
RXD
1. RXB event assumes receive buffers are 64 bytes each.
2. The RENA events, if required, must be programmed in the port C parallel I/O, not in the SCC itself.
3. The RXF interrupt may occur later than RENA due to receive FIFO latency.
1. TXB events assume the frame required two transmit buffers.
2. The GRA event assumes a GRACEFUL STOP TRANSMIT command was issued during frame transmission.
3. The TENA or CLSN events, if required, must be programmed in the port C parallel I/O, not in the SCC itself.
EVENTS
TRANSMITTED BY ETHERNET
RECEIVED IN ETHERNET
P = Preamble, SFD = Start Frame Delimiter, DA and SA = Source/Destination Address, T/L = Type/Length,
D = Data, and CR = CRC bytes.
TIME
FRAME
FRAME
LINE IDLE
LINE IDLE
Figure 7-72. Ethernet Interrupt Events Example
Freescale Semiconductor, Inc.
For More Information On This Product,
P
SFD
P
SFD DA SA T/L
DA SA T/L
MC68360 USER’S MANUAL
Go to: www.freescale.com
STORED IN RX BUFFER
TXB
TX BUFFER
STORED IN
D
RXB
D
CR
Serial Communication Controllers (SCCs)
CR
RXF
GRA
TXB
LINE IDLE
LINE IDLE
;
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