MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 639
![IC MPU QUICC 25MHZ 357-PBGA](/photos/6/76/67680/mfg_mpc860_series_sml.jpg)
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer:
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Serial Peripheral Interface (SPI)
When the SPI is working as a master, SPICLK is the clock output signal that shifts in the
received data from the SPIMISO pin and shifts out the transmitted data to the SPIMOSI pin.
Additionally, an SPI master device must provide a slave select signal output to enable the
SPI slave devices. This may be implemented using one of the QUICC’s general-purpose I/
O pins. The SPISEL pin should not be asserted while the SPI is working as a master, or the
SPI will indicate an error.
When the SPI is working as a slave, SPICLK is the clock input signal that shifts in the
received data from the SPIMOSI pin and shifts out the transmitted data to the SPIMISO pin.
The SPISEL pin provided by the QUICC is the enable input to the SPI slave.
When the SPI is working in a multi-master environment, the SPISEL pin is still an input and
is used to detect an error condition when more then one master is operating.
SPICLK is a gated clock (i.e., the clock only toggles while data is being transferred). The
user can select any of four combinations of SPICLK phase and polarity using two bits in the
SPI mode register (SPMODE).
The SPI pins can also be configured as open-drain pins to support a multi-master configu-
ration where the same SPI pin can be driven by the QUICC or an external SPI device.
7.12.4 SPI Transmit/Receive Process
The following paragraphs discuss SPI master, slave, and multi-master operation.
7.12.4.1 SPI MASTER MODE. When the SPI functions in master mode, the SPI transmits
a message to the peripheral (SPI slave), which in turn sends back a simultaneous reply.
When the QUICC works with more than one slave, it can use the general-purpose parallel
I/O pins to selectively enable different slaves.
To begin the data exchange, the CPU32+ core writes the data to be transmitted into a data
buffer, configures a Tx BD with its R-bit set and configures one or more Rx BDs. The
CPU32+ core should then set the STR bit in the SPCOM to start transmission of data. The
data will begin transmission once the SDMA channel has loaded the transmit FIFO with
data.
The SPI controller then generates programmable clock pulses on the SPICLK pin for each
character and shifts the data out on the SPIMOSI pin. At the same time, the SPI shifts
receive data in from the SPIMISO pin. This receive data is written into a receive buffer using
the next available Rx BD. The SPI will continue transmitting and receiving characters until
the transmit buffer has been completely transmitted or an error has occurred (SPISEL pin
unexpectedly asserted). The CP then clears the R and E bits in the Tx BD and Rx BD, and
issues a maskable interrupt to the CPM interrupt controller.
When multiple Tx BDs are ready for transmission, the Tx BD L-bit determines whether the
SPI continues to transmit without waiting for the STR bit to be set again. If the L-bit is
cleared, the data from the next Tx BD will begin its transmission following the transmission
of data from the first Tx BD. In most cases, the user should see no delay on the SPIMOSI
pin between buffers. If the L-bit is set, transmission will cease after data from this Tx BD has
MC68360 USER’S MANUAL
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