MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 347
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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REF—Output Reference Event
CAP—Capture Event
7.5.3 Timer Examples
The following example lists the required initialization sequence of timer 2 to generate an in-
terrupt every 10 s, assuming a general system clock of 25 MHz. This means that an inter-
rupt should be generated every 250 system clocks.
To implement the same function with a 32-bit timer using timer 1 and timer 2, the following
sequence may be used:
The counter has reached the TRR value. The ORI bit in the TMR is used to enable the
interrupt request caused by this event.
The counter value has been latched into the TCR. The CE bits in the TMR are used to
enable generation of this event.
1. TGCR = $0000. Put timer 2 into the reset state. Do not use cascaded mode.
2. TMR2 = $001A. Enable the prescaler of the timer to divide-by-1 and the clock source
3. TCN2 = $0000. Initialize the timer 2 count to zero. This is the default state of this reg-
4. TRR2 = $00FA. Initialize the timer 2 reference value to 250 (decimal).
5. TER2 = $FFFF. Clear TER2 of any bits that might have been set.
6. CIMR = $00040000. Enable the timer 2 interrupt in the CPM interrupt controller. Initial-
7. TGCR = $0010. Enable timer 2 to begin counting.
1. TGCR = $0080. Cascade timer 1 and timer 2. Put timer 1 and timer 2 in the reset state.
2. TMR2 = $001A. Enable the prescaler of timer 2 to divide-by-1 and the clock source to
3. TMR1 = $0000. Enable timer 1 to use the output of timer 2 as its input, which is the
4. TCN1 = $0000, TCN2 = $0000. Initialize the combined timer 1 and timer 2 count to
5. TRR1 = $0000, TRR2 = $00FA. Initialize the combined timer 1 and timer 2 reference
6. TER2 = $FFFF. Clear TER2 of any bits that might have been set.
7. CIMR = $00040000. Enable the timer 2 interrupt in the CPM interrupt controller. Initial-
8. TGCR = $0091. Enable timer 1 and timer 2 to begin counting. Leave the timers in cas-
to general system clock. Enable an interrupt when the reference value is reached, and
restart the timer to repeatedly generate 10- s interrupts.
ister.
ize the CPM interrupt configuration register.
general system clock. Enable an interrupt when the reference value is reached, and
restart the timer to repeatedly generate 10 s interrupts.
default state of this register.
zero which is the default state of this register. (This can be accomplished with one 32-
bit data move to TCN1.)
value to 250 (decimal). (This can be accomplished with one 32-bit data move to
TRR1.)
ize the CPM interrupt configuration register.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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