MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 362
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Exar
Quantity:
160
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC68360VR25VLR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 362 of 962
- Download datasheet (4Mb)
IDMA Channels
DE—Destination Access Bus Error
DA—Done Asserted During Transfer
Data Length
Source Buffer Pointer
Destination Buffer Pointer
7.6.4.2.3 IDMA Commands (INIT_IDMA). This command causes the RISC controller to
reinitialize its IDMA internal state to the condition it had after a system reset. The IDMA BD
pointer is reinitialized to the top of BD ring. When in the auto buffer and buffer chaining
modes, the IDMA can be reset by setting the RST bit in the CMR and issuing the INIT_IDMA
command. The INIT_IDMA command should only be executed in conjunction with the set-
ting of the RST bit in the CMR.
7.6.4.3 STARTING THE IDMA. Once the channel has been initialized with all parameters
required for a transfer operation, it is started by setting the STR bit in the CMR. After the
channel has been started, any register that describes the current operation may be read but
not modified (SAPR, DAPR, FCR, or BCR).
Once STR has been set, the channel is active and either accepts operand transfer requests
in external mode or generates requests automatically in internal mode. When the first valid
external request is recognized, the IDMA arbitrates for the bus. The DREQx input is ignored
until STR is set.
7-38
The buffer was closed due to a bus error on the destination access. An interrupt (BED)
will be generated, regardless of the I-bit. The RISC will clear the V-bit of this BD.
The buffer was closed due to the assertion of DONEx. An interrupt (DONE) will be gener-
ated, regardless of the I-bit. The RISC will clear the V-bit of this BD.
The data length is the number of bytes that the IDMA should transfer from/to this BD’s
data buffer. The data length should be programmed to a value greater than zero.
The source buffer pointer contains the address of the associated source data buffer. The
buffer may reside in either internal or external memory.
The destination buffer pointer contains the address of the associated destination data
buffer. The buffer may reside in either internal or external memory.
In single address mode when the source is a device, this field is
ignored. In dual address mode when the source is a device, this
field should contain the device address.
In single address mode when the destination is a device, this
field is ignored. In dual address mode when the destination is a
device, this field should contain the device address.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
NOTE
Related parts for MC68360VR25VL
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
MC68360 MC68360 Multiple Ethernet Channels on the QUICC
Manufacturer:
Motorola / Freescale Semiconductor
Part Number:
Description:
MC68360 Implementing an 8 bit Eprom for an MC68EC040-MC68360 System
Manufacturer:
Motorola / Freescale Semiconductor
Part Number:
Description:
MC68360 Interfacing the MC68060 to the MC68360
Manufacturer:
Motorola / Freescale Semiconductor
Part Number:
Description:
MC68360 MC68360 RAM Microcode Package Option Overview
Manufacturer:
Motorola / Freescale Semiconductor
Part Number:
Description:
MC68360 MC68360 CPM-CPU Interaction
Manufacturer:
Motorola / Freescale Semiconductor
Part Number:
Description:
MC68360 Interfacing SDRAM to the MC68360 QUICC Device
Manufacturer:
Motorola / Freescale Semiconductor
Part Number:
Description:
MC68360 Interfacing the QUICC to a MCM516400 (4Mx4 10-12 column-row) DRAM
Manufacturer:
Motorola / Freescale Semiconductor
Part Number:
Description:
MC68360 Interfacing the 68360 (QUICC) to T1-E1 Systems
Manufacturer:
Motorola / Freescale Semiconductor
Part Number:
Description:
MC68360 Multiple QUICC Design Concept
Manufacturer:
Motorola / Freescale Semiconductor
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
Part Number:
Description:
Manufacturer:
Freescale Semiconductor, Inc
Datasheet: