MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 636
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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Serial Peripheral Interface (SPI)
CRXB—C/I Channel Buffer Received
MTXB—Monitor Channel Buffer Transmitted
MRXB—Monitor Channel Buffer Received
7.11.14.10 SMC MASK REGISTER (SMCM). The SMCM is an 8-bit, memory-mapped,
read-write register. It has the same bit format as the SMC event register. If a bit in the SMCM
is a one, the corresponding interrupt in the SMC event register will be enabled. If the bit is
zero, the corresponding interrupt in the SMC event register will be masked. The SMCM is
clear upon reset.
7.12 SERIAL PERIPHERAL INTERFACE (SPI)
The SPI allows the QUICC to exchange data between other QUICC chips, the MC68302,
the M68HC11 and M68HC05 microcontroller families, and a number of peripheral devices
such as EEPROMs, real-time clock devices, A/D converters, and ISDN devices.
7.12.1 Overview
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire
interface (receive, transmit, clock, and slave select).
The SPI block consists of transmitter and receiver sections, an independent baud rate gen-
erator, and a control unit. The transmitter and receiver sections use the same clock, which
is derived from the SPI baud rate generator in master mode and generated externally in
slave mode. During an SPI transfer, data is transmitted and received simultaneously. Refer
to Figure 7-80 for the SPI block diagram.
7-312
The C/I receive buffer is full.
The monitor transmit buffer became empty.
The monitor receive buffer is full.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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