MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 327
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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7.1 RISC CONTROLLER
The RISC controller is the 32-bit central controller of the communication processor module
(CPM). Since its execution occurs on a separate bus that is hidden from the user, it does
not impact CPU32+ core performance. The RISC controller works with the serial channels
and parallel interface port (PIP) to implement the user-chosen protocols and to manage the
SDMA channels that transfer data between the SCCs and memory. The RISC controller
contains an internal timer that can be used to implement up to 16 additional timers for the
user application software. These features are collectively known as the communication pro-
cessor (CP), which is a subset of the overall CPM. Additionally, the RISC controller can
manage the operation of the IDMA channels, if desired. The 32-bit RISC handles the lower
layer tasks and DMA control activities, leaving the 32-bit CPU32+ core (or other external
processor) free to handle higher layer activities. Thus, the QUICC can be thought of as a
dual 32-bit processor system.
The RISC controller communicates with the host (CPU32+ core or other external processor)
in several ways. First, many parameters are exchanged through the dual-port RAM. In the
case of simultaneous accesses (at least one of which is a write operation), the RISC con-
troller may be delayed by one clock in its access to the dual-port RAM. The host is never
delayed. Second, the RISC controller can execute special commands issued by the host.
These commands are only required to be issued in special situations. Third, the RISC con-
troller can generate interrupts through the CPM interrupt controller. Fourth, status/event reg-
isters, which show events that have occurred within the RISC, may be read at any time by
the CPU32+ or an external processor.
The RISC controller has the ability to control a set of up to 16 timers. These timers are sep-
arate and distinct from the four general-purpose timers and baud rate generators in the
CPM. The 16 timers are ideally used in protocols that do not require extreme precision, but
in which it is desirable to off-load the host CPU from having to scan the timer tables that are
created in software. These timers are clocked from an internal timer used only by the RISC
controller.
The RISC controller uses the peripheral bus to communicate with all of its peripherals. Each
SCC has a separate receive and transmit FIFO. The SCC1 FIFOs are 32-bytes each; the
other SCC FIFOs are 16-bytes each. The SMC and SPI FIFO sizes are double-buffered.
The PIP is a single register interface.
The following priority scheme determines the processing priority of the RISC controller. It is
as follows:
1. Reset in CP Command Register or System Reset
2. DMA Bus Error
3. Commands Issued to the CP Command Register
4. CC1 Rx
5. SCC1 Tx
6. SCC2 Rx
7. SCC2 Tx
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
RISC Controller
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