MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 166
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
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MC68360VR25VL
Manufacturer:
Exar
Quantity:
160
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Freescale Semiconductor
Quantity:
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Part Number:
MC68360VR25VLR2
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CPU32+
5.3.3.7 BINARY-CODED DECIMAL (BCD) INSTRUCTIONS. Five
operations on BCD numbers. The arithmetic operations on packed BCD numbers are add
decimal with extend (ABCD), subtract decimal with extend (SBCD), and negate decimal with
extend (NBCD). Table 5-9 is a summary of the BCD operations.
5.3.3.8 PROGRAM CONTROL INSTRUCTIONS. A set of subroutine call and return
instructions and conditional and unconditional branch instructions perform program control
operations. Table 5-10 summarizes these instructions.
5-24
Instruction
Instruction
BCHG
ABCD
NBCD
SBCD
BCLR
BSET
BTST
– (An), – (An)
– (An), – (An)
# data
# data
# data
# data
Table 5-9. Binary-Coded Decimal Operations
Operand
Operand
Dn, ea
Dn, ea
Dn, ea
Dn, ea
Syntax
Syntax
Dn, Dn
Dn, Dn
ea
Table 5-8. Bit Manipulation Operations
Freescale Semiconductor, Inc.
For More Information On This Product,
ea
ea
ea
ea
MC68360 USER’S MANUAL
Go to: www.freescale.com
Operand
Operand
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
Size
Size
8
8
8
8
8
8
~( bit number of destination)
~( bit number of destination)
~( bit number of destination)
~ bit number of destination)
Source 10 + Destination 10 + X
0 – Destination 10 – X
Destination 10 – Source 10 – X
destination
destination
destination
Operation
Operation
Destination
instructions
Z
Z; 0
Z; 1
Z
Destination
Destination
bit of
bit of
bit of
support
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