MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 258
![IC MPU QUICC 25MHZ 357-PBGA](/photos/6/76/67680/mfg_mpc860_series_sml.jpg)
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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System Integration Module (SIM60)
divided prior to being used by any QUICC on-chip module). Furthermore, the divide-by-128
function allows the value of the final system frequency to be chosen with much greater pre-
cision, since it is a multiple of ~32 kHz rather than a multiple of ~4 MHz.
The choice of whether to use the divide-by-128 function is made with the MODCK1–
MODCK0 pins. This resulting frequency is called CLKIN.
6.5.3 Phase-Locked Loop (PLL)
The PLL takes the CLKIN frequency and outputs a high-frequency source used to derive the
general system frequency of the QUICC. The PLL is comprised of a phase detector, loop
filter, voltage-controlled oscillator (VCO), and multiplication block. The VCO output can be
as high as 50 MHz for a 25-MHz QUICC.
The PLL’s main functions are frequency multiplication and skew elimination.
6.5.3.1 FREQUENCY MULTIPLICATION. The PLL can multiply the CLKIN input frequency
by any integer between 1 and 4096. The output of the VCO is twice the QUICC system fre-
quency after reset.
If a low frequency crystal is chosen (e.g., ~32 kHz), the multiplier defaults to 401, giving a
2 VCO output of ~26 MHz and an initial general system clock of ~13 MHz. The multiplica-
tion factor may then be changed to the desired value by writing the MF11–MF0 bits in the
PLLCR. When the PLL multiplier is modified in software, the PLL will lose lock, and the
clocking to the QUICC will stop until lock is regained (worst case is 2500 clocks; typical case
is 500 clocks). See 6.5.4 Low-Power Divider for methods of reducing clock rates without los-
ing lock.
6-14
NOTE:
20 pF
1. Must be low-leakage capacitor. See Section 10 Electrical Characteristics for recommended values.
2. Values are for 32 kHz crystal and may vary due to capacitance on PCB.
EXTAL
OSCILLATOR
CRYSTAL
CRYSTAL 2
20 M
XTAL
20 pF
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 6-6. External Components
XFC PIN
MC68360 USER’S MANUAL
Go to: www.freescale.com
GENERATION
CLOCK
390nF
XFC
VCCSYN
1
VCCSYN
0.01 F
0.1 F
GNDSYN
VCCCLK
CLKO1
CLKO2
0.1 F
GNDCLK
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