MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 199
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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frames of other M68000 family members. The only internal machine state required in the
CPU32+ stack frame is the bus controller state at the time of the error and a single register.
Bus operation in progress at the time of a fault is conveyed by the SSW.
The bus error stack frame is 12 words in length. There are three variations of the frame, each
distinguished by different values in the SSW TP and MV fields.
An internal transfer count register appears at location SP + $14 in all bus error stack frames.
The register contains an 8-bit microcode revision number and, for type III faults, an 8-bit
transfer count. Register format is shown in Figure 5-14.
The microcode revision number is checked before a bus error stack frame is restored via
RTE. In a multiprocessor system, this check ensures that a processor using stacked infor-
mation is at the same revision level as the processor that created it.
The transfer count is ignored unless the MV bit in the stacked SSW is set. If the MV bit is
set, the least significant byte of the internal register is reloaded into the MOVEM transfer
counter during RTE execution.
For faults occurring during normal instruction execution (both prefetches and non-MOVEM
operand accesses), SSW TP,MV = 00. Stack frame format is shown in Figure 5-15.
Faults that occur during the operand portion of the MOVEM instruction are identified by SSW
TP,MV = 01. Stack frame format is shown in Figure 5-16.
When a bus error occurs during exception processing, SSW TP,MV = 10. The frame shown
in Figure 5-17 is written below the faulting frame. Stacking begins at the address pointed to
by SP – 6 (SP value is the value before initial stacking on the faulted frame).
The frame can have either four or six words, depending on the type of error. Four-word stack
frames do not include the faulted instruction PC. (The internal transfer count register is
located at SP
The fault address of a dynamically sized bus cycle is the address of the upper byte, regard-
less of the byte that caused the error.
TP
15
15
MV
14
SZC1
MICROCODE REVISION NUMBER
13
$10 and the SSW is located at SP
TR
12
Figure 5-14. Internal Transfer Count Register
Freescale Semiconductor, Inc.
11
B1
For More Information On This Product,
B0
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
RR
9
RM
8
8
IN
7
7
$12.)
RW
6
SZC0
5
TRANSFER COUNT
4
SIZ
3
2
FUNC
1
CPU32+
0
0
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