MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 563
![IC MPU QUICC 25MHZ 357-PBGA](/photos/6/76/67680/mfg_mpc860_series_sml.jpg)
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Exar
Quantity:
160
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC68360VR25VLR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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7.10.23.4 CONNECTING QUICC TO ETHERNET. Figure 7-67 shows the basic compo-
nents and pins required to make the Ethernet connection between the QUICC and the
EEST.
The QUICC Ethernet controller has seven basic pins that make up the interface to the ex-
ternal EEST chip:
5. 7.10.23 Ethernet Controller should be read next.
6. 7.15 CPM Interrupt Controller (CPIC) defines the interrupt priority of this SCC and how
7. 7.14 Parallel I/O Ports shows how to configure the desired Ethernet pin functions to be
1. Receive clock. Receive clock to the SCC (RCLK) may be either the CLK1, CLK2,
2. Transmit clock. Transmit clock to the SCC (TCLK) may be either the CLK1, CLK2,
3. Transmit data. This is the QUICC the TXD pin.
4. Receive data. This is the QUICC RXD pin.
cable to all protocols. The reader does not need to read the SCC DPLL description
since the on-chip DPLLs are not used in Ethernet.
interrupts are generated to the CPU32+ core.
active.
CLK3, or CLK4 pin that is routed through the bank of clocks on the QUICC.
CLK3, or CLK4 pin that is routed through the bank of clocks on the QUICC. (The SCC
RCLK and SCC TCLK should not be connected to the same CLKx pin since the EEST
provides a separate receive and transmit clock signal).
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Communication Controllers (SCCs)
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