MC68360VR25VL Freescale Semiconductor, MC68360VR25VL Datasheet - Page 517
![IC MPU QUICC 25MHZ 357-PBGA](/photos/6/76/67680/mfg_mpc860_series_sml.jpg)
MC68360VR25VL
Manufacturer Part Number
MC68360VR25VL
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360VR25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Exar
Quantity:
160
Company:
Part Number:
MC68360VR25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC68360VR25VLR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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To ensure that all stations gain an equal share of the bus, a priority mechanism is also imple-
mented in HDLC bus. Once an HDLC bus node has completed the transmission of a frame,
it waits for 10 consecutive one bits, rather than just 8, before beginning the next transmis-
sion. In this way, all nodes desiring to transmit will obtain the bus, before a node transmits
twice. Once a node detects that 10 consecutive ones have occurred on the bus, it may
attempt transmission and can reinstate its original priority of waiting for 8 ones.
7.10.18.2.2 More Performance. Since HDLC bus is used in a wired-OR configuration, the
limit of HDLC bus operation is determined by the rise time of the one bit.
Figure 7-57 shows a method to increase performance. The user supplies a clock that is high
for a shorter duration than it is low, which allows more rise time in the case of a one bit.
(OUTPUT)
(INPUT)
TCLK
TXD
CTS
(OUTPUT)
(INPUT)
TCLK
TXD
CTS
Figure 7-56. HDLC Bus Collision Detection
Figure 7-57. Non-Symmetrical Duty Cycle
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Communication Controllers (SCCs)
CTS SAMPLED AT HALFWAY POINT.
COLLISION DETECTED WHEN
TXD = 1, BUT CTS = 0.
CTS sampled at three quarter point.
Collision detected when
TXD = 1, but CTS = 0.
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