VSC8211XVW Vitesse Semiconductor Corp, VSC8211XVW Datasheet - Page 112

• Manufacturer Part Number: VSC8211XVW
• Description: IC PHY 10/100/1000 SGL 117-LBGA
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8211XVW

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 117-LBGA
• Case: BGA
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1023

VSC8211
Datasheet
1
24.6:4 – RX FIFO Depth Control
Used in 1000BT Serial MAC, SGMII, and RTBI modes only, bits 24.6:4 control symbol buffering as determined by the receive
synchronization FIFO. An internal FIFO is used to synchronize the clock domains between the MAC receive clock and the
PHY’s clock (e.g., REFCLK), used to receive symbols on the local PHY’s twisted pair interface.
The IEEE mode supports up to 1518-byte packet size with the minimum inter-packet gap (IPG). The jumbo packet mode adds
latency to the path to support up to 9600-byte packets with the minimum inter-packet gap (IPG). When using jumbo packet
mode, a larger IPG is recommended due to the possible compression of the IPG at the output of the FIFO.
24.3:1 – Reserved
2
24.0 - Connector Loopback
See
Section 18.5: "Connector Loopback"
for details.
1
The TX and RX FIFOs are not used in MII mode for 10BASE-T and 100BASE-TX.
2
MII Register bit 18.5
must also be set to enable this feature.
112 of 165
VMDS-10105 Revision 4.1
October 2006