VSC8211XVW Vitesse Semiconductor Corp, VSC8211XVW Datasheet - Page 64

• Manufacturer Part Number: VSC8211XVW
• Description: IC PHY 10/100/1000 SGL 117-LBGA
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8211XVW

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 117-LBGA
• Case: BGA
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1023

18 Advanced Test Modes
18.1 1000BASE-T Ethernet Packet Generator (EPG)
For system-level debugging and in-system production testing, the VSC8211 includes an Ethernet packet generator. This can be
used to isolate problems between the MAC and PHY and between a local PHY and remote link partner. It is intended for use
with lab testing equipment or in-system test equipment only, and should not be used when the VSC8211 is connected to a live
network.
To use the EPG, it must be enabled by writing a “1” to Extended MII Register 29E.15. This effectively disables all MAC-interface
transmit pins and selects the EPG as the source for all data transmitted onto the VSC8211 media interface. For this reason,
packet loss will occur if the EPG is enabled during transmission of packets from MAC to PHY. The MAC receive pins will still be
active when the EPG is enabled, however. If it is necessary to disable the MAC receive pins as well, this can be done by writing
a “1” to MII Register bit 0.10.
When a “1” is written to Extended MII Register Bit 29E.14, the VSC8211 will begin transmitting IEEE802.3 layer-2 compliant
packets with a data pattern of repeating 16-bit words as specified in Extended MII Register 30E. The source and destination
addresses for each packet, packet size, interpacket gap, FCS state, and transmit duration can all be controlled through
Extended MII Register 29E. Note that if Extended MII Register Bit 29E.13 is cleared, Extended MII Register Bit 29E.14 will be
cleared automatically after 30,000,000 packets have been transmitted.
18.2 1000BASE-T CRC Counter
When the EPG is enabled, a bad-CRC counter is also available for all incoming packets. This counter is available in Extended
MII Register Bits 23E.7:0 - CRC Counter and is automatically cleared when read.
18.3 Far-end Loopback
Far-end loop back mode, when enabled (MII Register bit 23.3 = 1), forces incoming data from a link partner on the current
media interface to be retransmitted back to the link partner on the media interface as shown in the figure below. In addition, the
incoming data will also appear on the receive data pins of the MAC interface. Data present on the transmit pins of the MAC
interface are ignored in this mode. This loop back mode is available in both Serial and Parallel MAC PHY operating modes. For
more information, refer to
18.4 Near-end Loopback
When Near-end loop back is set
the Receive Data (RXD) pins to the MAC as shown in the figure below. In this mode, no signal is transmitted over the network
media. This loop back mode in available in both Serial MAC and Parallel MAC PHY Operating modes.
VMDS-10105 Revision 4.1
October 2006
Link Partner
“Register 23 (17h) – PHY Control Register #1”
CAT-5 or Fiber
(MII Register bit 0.14 =
Figure 31. Far-end Loopback Block Diagram
RX
TX
1), the Transmit Data (TXD) on the MAC interface is looped back onto
64 of 165
VSC8211
on page 108.
RXD
TXD
MAC
Datasheet
VSC8211