VSC8211XVW Vitesse Semiconductor Corp, VSC8211XVW Datasheet - Page 74

• Manufacturer Part Number: VSC8211XVW
• Description: IC PHY 10/100/1000 SGL 117-LBGA
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8211XVW

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 117-LBGA
• Case: BGA
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1023

Using the EEPROM data format shown in
locations from the EEPROM. If the PHYs have to be initialized differently, then the 'Address pointers' will differ for each PHY,
along with different PHY configuration data values.
VMDS-10105 Revision 4.1
October 2006
{bpage_addr2,s_
{bpage_addr1,s_
Table 28. Configuration EEPROM Data Format (continued)
7,263,519,..
6,262,518,..
5,261,517,..
4,260,516,..
3,259,515,..
2,258,514,..
0,256,512...
1,257,513..
addr2} = M
addr1} = N
-------------
-------------
-------------
-------------
-------------
-------------
Address
M+7
M+6
M+5
M+4
M+3
M+2
M+1
N+7
N+6
N+5
N+4
N+3
N+2
N+1
Table 28
----------------------------------------------------
----------------------------------------------------
----------------------------------------------------
----------------------------------------------------
Data to be written (LSB)
Data to be written (MSB)
RegAddress b
Data to be written (LSB)
Data to be written (MSB)
RegAddress a
Number of PHY Register writes *3[15:8]
----------------------------------------------------
Data to be written (LSB)
Data to be written (MSB)
RegAddress b
Data to be written (LSB)
Data to be written (MSB)
RegAddress a
Number of PHY Register writes *3[7:0]
----------------------------------------------------
{PHY Address 1[4:0], 3’bpage_addr3}
{PHY Address 2[4:0], 3’bpage_addr2}
{PHY Address 1[4:0], 3’bpage_addr1}
8’hBD
8’hBD
Number of PHY Register writes *3[7:0]
Number of PHY Register writes *3[15:8]
Starting address for initializing PHY3 s_addr3
Starting address for initializing PHY2 s_addr2
Starting address for initializing PHY1 s_addr1
enables multiple PHYs to be initialized in a similar way by reading the same
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