VSC8211XVW Vitesse Semiconductor Corp, VSC8211XVW Datasheet - Page 85

• Manufacturer Part Number: VSC8211XVW
• Description: IC PHY 10/100/1000 SGL 117-LBGA
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8211XVW

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 117-LBGA
• Case: BGA
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1023

1
2
25.3 MII Register Descriptions
25.3.1 Register 0 (00h) – Mode Control Register - Clause 28/37 View
0.15 – Software Reset
Writing a “1” to bit 0.15 initiates a software reset. Once Software Reset is asserted, the PHY is returned to normal operating
mode and is ready for the next SMI transaction, so Software Reset always reads back “0”. Software Reset restores all SMI
registers to their default states, except for registers marked with an “S” or “SS” in the sticky column.
0.14 – Near End Loopback
When the Near End Loopback bit is set, the Transmit Data (TXD) on the MAC interface is looped back onto the Receive Data
(RXD) pins to the MAC. In this mode, no signal is transmitted over the network media. The loopback mechanism works in all
(10/100/1000) modes of operation. The operating mode is determined by bits 0.13 and 0.6 (forced speed selection). See
section 18.4, “Near-end Loopback,”
0.13, 0.6 – Forced Speed Selection
These bits determine the 10/100/1000 speed when Auto-Negotiation is disabled by clearing control
ignored if control
VMDS-10105 Revision 4.1
October 2006
Bit
15
14
6, 13
12
11
10
9
8
7
6
5:0
In MSA mode, when this bit is set, the PHY does not return the correct values for the subsequent register read operations. In order to read the correct PHY register
When this bit is set, while the PHY is operating in one of the ‘Serial MAC/TBI/RTBI to CAT5 Media’ category of PHY operating modes. The PHY will drop the CAT5
values, the station manager must provide 70 clock cycles on the MODDEF1/MDC pin or perform two byte read operations on any eeprom address other than in
page ‘110’ immediately following s/w reset.
Media link. Also, setting of this bit will not disable the clock output on SCLKP and SCLKN pins.
Register 0 (00h) – Mode Control Register - Clause 28/37 View
Name
Software Reset
Near End Loopback
Forced Speed Selection
Auto-Negotiation Enable
Power-Down
Isolate
Restart Auto-Negotiation
Duplex Mode
Collision Test Enable
MSB for Speed Selection
(see bit 13 above)
Reserved
2
bit 0.12
1
is set. These bits also determine the operating mode when Near End Loopback (bit 0.14) is set.
page 64 for more information.
Access
R/W SC
R/W
R/W
R/W
R/W
R/W
R/W SC
R/W
R/W
R/W
RO
States
1 = Reset asserted
0 = Reset de-asserted
1 = Near End Loopback on
0 = Near End Loopback off
00 = 10Mbps
01 = 100Mbps
10 = 1000Mbps
11 = Reserved
1 = Auto-Negotiation enabled
0 = Auto-Negotiation disabled
1 = Power-down
0 = Power-up
1 = Disable Parallel MAC outputs
0 = Normal Operation
1 = Restart MII
0 = Normal operation
1 = Full duplex
0 = Half duplex
1 = Collision test enabled
0 = Collision test disabled
See “Forced Speed Selection” Above
85 of 165
Reset Value
0
0
10
1
0
0
0
0
0
1
000000
bit
0.12. These bits are
Datasheet
Sticky
VSC8211