VSC8211XVW Vitesse Semiconductor Corp, VSC8211XVW Datasheet - Page 58

• Manufacturer Part Number: VSC8211XVW
• Description: IC PHY 10/100/1000 SGL 117-LBGA
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8211XVW

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 117-LBGA
• Case: BGA
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1023

The PHY also includes the optional Device Identification Register, shown in the following table, which allows the manufacturer,
part number, and version number of the device to be determined through the TAP Controller.
See Chapter 11 of the IEEE 1149.1-1990 specifications for more details. Also, note that some of the information in the
identification register is duplicated in the IEEE-specified bit fields in MII Register 3 (PHY Identifier Register #2).
15.1 Supported Instructions and Instruction Codes
After a TAP reset, the Device Identification Register is serially connected between TDI and TDO by default. The TAP Instruction
Register is loaded either from a shift register (when a new instruction is shifted in), or, if there is no new instruction in the shift
register, a hard-wired default value of 0110 (IDCODE) is loaded. Using this method, there is always a valid code in the
instruction register, and the problem of toggling instruction bits during a shift is avoided. Unused codes are mapped to the
BYPASS instruction.
The VSC8211 supports the instruction codes listed in the following table and described below.
EXTEST
The mandatory EXTEST instruction allows testing of off-chip circuitry and board-level interconnections by sampling input pins
and loading data onto output pins. Outputs are driven by the contents of the boundary-scan cells, which have to be updated with
valid values (with the PRELOAD instruction) prior to the EXTEST instruction.
SAMPLE/PRELOAD
The mandatory SAMPLE/PRELOAD instruction allows a snapshot of inputs and outputs during normal system operation to be
1
VMDS-10105 Revision 4.1
October 2006
Instruction
EXTEST
SAMPLE/PRELOAD
IDCODE
CLAMP
HIGHZ
BYPASS
Reserved
Following the use of this instruction, the on-chip system logic may be in an indeterminate state that will persist until a system reset is applied.
Therefore, the on-chip system logic may need to be reset on return to normal (i.e., non-test) operation.
Description
Bit Field
Binary Value 0001
0001
Code
0000
0110
0010
0011
0111
0100, 1000,
1001, 1010,
1011, 1100,
1101, 1110,
1111
Device Version Number
(or Revision Code)
31 - 28
Table 23. JTAG Device Identification Register Description
Selected Register
Boundary-Scan Register
Boundary-Scan Register
Device Identification Register
Bypass Register
Bypass Register
Bypass Register
Table 24. JTAG Interface Instruction Codes
Part Number
(or Model Number)
27 - 12
1000 0010 0001 0001
58 of 165
1
Register Width
78
78
1
32
1
1
Vitesse’s
Manufacturer Identity
11 - 1
001 1001 1000
Specification
Mandatory IEEE 1149.1
Mandatory IEEE 1149.1
Optional IEEE 1149.1
Optional IEEE 1149.1
Optional IEEE 1149.1
Mandatory IEEE 1149.1
LSB
0
1
Datasheet
VSC8211