VSC8211XVW Vitesse Semiconductor Corp, VSC8211XVW Datasheet - Page 70

• Manufacturer Part Number: VSC8211XVW
• Description: IC PHY 10/100/1000 SGL 117-LBGA
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8211XVW

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 117-LBGA
• Case: BGA
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1023

VMDS-10105 Revision 4.1
October 2006
Condition Parameter
SFP Mode Disable
SIGDET pin
direction
SerDes Line
Impedance
SQE Enable
10BASE-T Echo On
MII Register View
PICMG Miser Mode
Enable
PHY Operating
Name
CMODE3[2]
CMODE3[1]
CMODE4[0]
CMODE6[3]
CMODE Pin Name and Bit
CMODE1[3]
CMODE1[1]
CMODE1[0]
Table 27. PHY Operating Condition Parameter Description (continued)
Position
Value
This CMODE bit sets the default value of
0
1
The value of this bit is valid in non-SFP mode when CMODE bit
CMODE1[3] is 1. This CMODE bit sets the direction of the SIGDET pin by
setting the default value of Extended MII Register 19E.1
0
1
Sets the internal end termination resistance value of the Serial MAC/
Media Interface Input pins.
0
1
Sets the default value of
0
1
Sets the default value of
0
1
Sets the default Register View of the standard IEEE specified Registers
(MII Register 0 through MII Register 15).
0
1
Sets the default value of
reduces power consumption. This mode is suitable for applications where
the signal to noise ratio on the CAT-5 media is high, such as ethernet over
the backplane.
See
based Backplanes"
0
1
Section 12: "Transformerless Operation for PICMG 2.16 and 3.0 IP-
70 of 165
This sets
Sets the following PHY defaults:
• TXDIS/SRESET is active high i.e. behaves like TXDIS.
• MODDEF0/CLKOUTMAC pin functions like MODDEF0 i.e this pin
• RXLOS/SIGDET pins functions like the RXLOS.
• The SMI interface is set in MSA mode.
This sets
Sets the following PHY defaults:
• TXDIS/SRESET is active low i.e. behaves like SRESET.
• MODDEF0/CLKOUTMAC pin functions like CLKOUTMAC i.e this
• RXLOS/SIGDET pin functions like SIGDET.
• The SMI interface is set in IEEE mode.
Input
Output
50 Ω
75Ω
SQE Disabled
SQE Enabled
10BASE-T Echo disabled
10BASE-T Echo Enabled
Clause 28 view (specified for 1000BASE-T devices)
Clause 37 view (specified for 1000BASE-X devices)
PICMG Miser Mode Disabled
PICMG Miser Mode Enabled
is asserted low by the PHY once the EEPROM interface is
released for access through the SMI interface.
pin drives out a 125Mhz clock.
MII Register 21E.15
MII Register 21E.15
on page 45 for more information.
(MII Register 22.12
(MII Register 22.12
MII Register
MII Register
MII Register
(MII Register 22.13
(MII Register 22.13
Description
= 1.
= 0.
24.12. Putting the PHY in this mode
22.12.
22.13.
= 0)
MII Register 21E.15.
= 1)
= 0)
= 1)
Datasheet
VSC8211