VSC8211XVW Vitesse Semiconductor Corp, VSC8211XVW Datasheet - Page 151

• Manufacturer Part Number: VSC8211XVW
• Description: IC PHY 10/100/1000 SGL 117-LBGA
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8211XVW

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 117-LBGA
• Case: BGA
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1023

The RGMII specification (v2.0) defines the relationship shown above between the clock and data signals at the MAC/PHY
interface.
To meet this timing specification, a 1.5ns delay to the TXCLK and RXCLK signals is typically added on the PC board using a
long “trombone shaped” trace.
The VSC8211 includes an optional mode of operation where this PCB delay is handled internally (on-chip). This operating mode
can be enabled by setting
controlled to be 0ns, 1.5ns, 2.0ns, or 2.5ns. When the internal delay feature is used, the PHY is said to be in “RGMII
Compensated Mode”.
VMDS-10105 Revision 4.1
October 2006
RXC (at transmitter)
TXC (at transmitter)
RXC (at receiver)
TXC (at receiver)
RX[8:5][3:0]
RD[7:4][3:0]
TD[7:4][3:0]
TX[8:5][3:0]
RX[9]RX[4]
TX[9]TX[4]
RXCTL
TXCTL
Figure 43. RGMII/RTBI Uncompensated AC Timing and Multiplexing
MII Register
23.11:8. The internal delay on the TXCLK and RXCLK clocks can be independently
T
80%
20%
R
, T
F
TX[3:0]
TD[3:0]
RX[3:0]
RD[3:0]
TX[4]
TXEN
RX[4]
RXDV
151 of 165
VDDIOMAC/2
T
T
T
TX[9]
TXER
RX[9]
RXER
TX[8:5]
TD[7:4]
RX[8:5]
RD[7:4]
T
SKEW
SKEW
SKEW
SKEW
T
T
CYC
R
R
T
VDDIOMAC/2
Datasheet
VSC8211