VSC8211XVW Vitesse Semiconductor Corp, VSC8211XVW Datasheet - Page 68

• Manufacturer Part Number: VSC8211XVW
• Description: IC PHY 10/100/1000 SGL 117-LBGA
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8211XVW

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 117-LBGA
• Case: BGA
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1023

Each of the PHY Operating Condition Parameters mentioned in the Table 26 above is described in detail in Table 27.
VMDS-10105 Revision 4.1
October 2006
Condition Parameter
PHY Address[4:0]
PHY Operating
Mode[3:0]
LED Control[1:0]
Pulsing Enable
PHY Operating
Name
CMODE Pin Name and Bit
CMODE1[2],CMODE0[3:0]
CMODE2[3:0]
CMODE3[3],CMODE4[3]
CMODE4[2]
Table 27. PHY Operating Condition Parameter Description
Position
Value
31-0
These CMODE bits set the default PHY Operating Mode by setting the
default values of MII Register 23 bits 15:12 and 2:1. For more information,
see
0000 802.3z SerDes to CAT5 Media, Clause 37 auto-negotiation auto-
0001 RGMII with Copper/Fiber Auto Media Sense (Fiber Preference).
0010 GMII to Fiber.
0011 GMII/MII with Copper/Fiber Auto Media Sense (Fiber Preference).
0100 802.3z SerDes to CAT5 Media, Clause 37 disabled.
0101 SGMII to CAT5 Media, SCLK enabled.
0110 RGMII to CAT5 Media.
0111 RGMII to Fiber Media.
1000 GMII/MII to CAT5 Media.
1001 TBI to CAT5 Media, Clause 37 auto-negotiation auto-sense
1010 802.3z SerDes to CAT5 Media, Media Converter Mode.
1011 TBI to Fiber Media.
1100 RTBI to CAT5 Media, Clause 37 auto-negotiation auto-sense
1101 Serial MAC to Fiber Media, SCLK enabled.
1110 802.3z SerDes to CAT5 Media, Clause 37 enabled.
1111
This sets the default behavior of the LED pins LED[4:0] by setting the star-
tup values of MII
00
01
10
11
This sets the default power saving mode of the LED pins LED[4:0] by set-
ting the startup value of MII Register bit 27.4
1
0
Register 23 (17h) – PHY Control Register
68 of 165
Sets the PHY Address used to access the PHY Registers when the
PHY’s SMI is in IEEE mode. The value latched is reflected in
ister 23E (17h) - Extended PHY Control Register
bits 23.15:11.
sense enabled.
enabled.
enabled.
SGMII to CAT5 Media, SCLK disabled.
LED[4:0] = {Duplex/Collision, Link/Activity, Link10/Activity, Link100/
Activity, Link1000/Activity}(MII Reg 27 = 0000h)
LED[4:0] - {Activity, Duplex/Collision, Duplex/Collision, Link10/100/
Activity, Link/Activity} (MII Reg 27 = 5540h)
LED[4:0] - {Link Fault, Fiber Media Selected, Link/Activity, Link/
Activity, Fault} (MII Reg 27 = AA80h)
LED[4:0] - {Tx, Rx, Tx, Link100/1000/Activity, Rx} (MII Reg 27 =
FFC0h)
Enable 5Khz, 20% duty cycle LED pulsing for power savings
LED pulsing disabled
“Register 27 (1Bh) – LED Control Register”
Description
#1, page 108.
#4, page 129,
on page 117.
Datasheet
VSC8211
Reg-