VSC8211XVW Vitesse Semiconductor Corp, VSC8211XVW Datasheet - Page 121

• Manufacturer Part Number: VSC8211XVW
• Description: IC PHY 10/100/1000 SGL 117-LBGA
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8211XVW

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 117-LBGA
• Case: BGA
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1023

VSC8211
Datasheet
30.11 - MAC Asymmetric Pause
Bit 30.11 corresponds to the Asymmetric Pause bit sent to the VSC8211 by the MAC during the clause 37 auto-negotiation
process.
30.10 - MAC Symmetric Pause
Bit 30.10 corresponds to the Symmetric Pause bit sent to the VSC8211 by the MAC during the clause 37 auto-negotiation
process.
30.9 - Clause 37 Restart Autonegotiation
When bit 30.9 is set to a “1”, the clause 37 auto-negotiation process is restarted. This bit is self-clearing and always reads back
as “0”.
30.8 - MAC Full Duplex
Bit 30.8 corresponds to the Full Duplex Ability bit sent to the VSC8211 by the MAC during the clause 37 auto-negotiation
process.
30.7 - MAC Half Duplex
Bit 30.7 corresponds to the Half Duplex Ability bit sent to the VSC8211 by the MAC during the clause 37 auto-negotiation
process.
30.6 - Reserved
30.5 - Clause 37 Autonegotiation Complete
When bit 30.5 is set to a “1”, the clause 37 auto-negotiation has completed successfully.
30.4 - Reserved
30.3 - Link Interlock Fail
Bit 30.3 is set to indicate a failure to complete interlock between Clause-37 auto-negotiation and Clause-28 auto-negotiation.
This bit is valid only in SerDes to CAT5 PHY operating modes.
30.2 - Link Interlock Complete
Bit 30.2 is set to indicate a complete interlock between Clause-37 auto-negotiation and Clause-28 auto-negotiation. This bit is
valid only in SerDes to CAT5 PHY operating modes.
30.1:0 - RXLOS Pulse Delay
Bits 30.1:0 specify the RXLOS Pulse Delay. It sets the time the RXLOS/SIGDET signal pin is asserted when the CAT5 Media
Link is dropped. This bit is only valid when the ‘SFP Mode’ bit
Extended MII Register 21E.15 =
“1”.
121 of 165
VMDS-10105 Revision 4.1
October 2006