VSC8211XVW Vitesse Semiconductor Corp, VSC8211XVW Datasheet - Page 57

• Manufacturer Part Number: VSC8211XVW
• Description: IC PHY 10/100/1000 SGL 117-LBGA
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8211XVW

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 117-LBGA
• Case: BGA
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1023

15 Test Mode Interface (JTAG)
The PHY supports the Test Access Port and Boundary Scan Architecture IEEE 1149.1 standards. The device includes an IEEE
1149.1 compliant test interface, often referred to as a “JTAG TAP Interface”. IEEE 1149.1 defined test logic provides the
following standardized test methodologies:
The JTAG Test interface logic on the PHY, accessed through a Test Access Port (TAP) interface, consists of a boundary-scan
register and other logic control blocks. The TAP controller includes all IEEE-required signals (TMS, TCK, TDI, and TDO), in
addition to the optional asynchronous reset signal TRST.
The following figure diagrams the TAP and Boundary Scan Architecture.
VMDS-10105 Revision 4.1
October 2006
• Testing the interconnections between integrated circuits once they have been assembled onto a printed
circuit board or other substrate.
• Testing the integrated circuit itself during IC and systems manufacture.
• Observing or modifying circuit activity during the component’s normal operation.
TDI
TMS
TRSTz
TCK
Figure 28. Test Access Port and Boundary Scan Architecture
Test Access Port
Controller
Device Identification
Instruction Register,
Instruction Decode,
Bypass Register
Boundary-Scan
Register
Register
Control
control
select
tdoenable
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control
Mux,
DFF
TDO
Datasheet
VSC8211