VSC8211XVW Vitesse Semiconductor Corp, VSC8211XVW Datasheet - Page 99

• Manufacturer Part Number: VSC8211XVW
• Description: IC PHY 10/100/1000 SGL 117-LBGA
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8211XVW

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 117-LBGA
• Case: BGA
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1023

10.15 – MASTER/SLAVE Configuration Fault
This bit indicates whether a MASTER/SLAVE configuration fault has been detected by the local PHY. A configuration fault
occurs if both the local and remote PHYs are forced to the same MASTER/SLAVE state, or if no resolution is reached after
seven retries. When such a fault has been detected, this bit is set to “1”, but the PHY continues to renegotiate until the
MASTER/SLAVE configuration is resolved. Once set, this bit is automatically cleared when (and only when) Register 10 is read
via the SMI.
10.14 – MASTER/SLAVE Configuration Resolution
By default, the MASTER/SLAVE configuration is determined as part of the Auto-Negotiation process. However, the MASTER/
SLAVE status can optionally be manually forced via bits in MII
configuration status for the local PHY. This bit can change state only as a result of the reset or subsequent restart of the Auto-
Negotiation process. This bit is only valid when the
10.13 – Local Receiver Status
Bit 10.13 indicates the state of the loc_rcvr_status flag within the PMA receive function within the local PHY.
10.12 – Remote Receiver Status
Bit 10.12 indicates the state of the rem_rcvr_status flag within the PMA receive function within the local PHY.
10.11 – LP 1000BASE-T FDX Capability
Bit 10.11 is set to “1” if the Link Partner PHY advertises 1000BASE-T FDX capability. Otherwise, this bit is set to “0”. This bit is
valid on when
10.10 – LP 1000BASE-T HDX Capability
Bit 10.10 is set to “1” if the Link Partner PHY advertises 1000BASE-T HDX capability. Otherwise, this bit is set to “0”. This bit is
valid on when
10.9:8 – Reserved
10.7:0 – Idle Error Count
Bits 10.7:0 indicate the Idle Error count, where 10.7 is the most significant bit. These bits contain a cumulative count of the
errors detected when the receiver is receiving idles and PMA_TXMODE.indicate is equal to SEND_N (indicating that both the
local and remote receiver status have been detected to be OK). The counter is incremented every symbol period that
rx_error_status in the PMA receive function is equal to ERROR. Bits 10.7:0 are reset to all “0”s when the error count is read by
the management function, or upon execution of the PCS reset function, and they are saturated to all “1”s in case of overflow.
2
1
2
3
VMDS-10105 Revision 4.1
October 2006
The bits in this register apply only in 1000BASE-T mode.
This bit is valid only when the Page Received bit (6.1) is set to a “1”.
This bit applies only in 1000BASE-T mode.
The state of this bit is valid only if
MII Register 1.5
MII Register 1.5
3
is set.
is set.
MII Register 9.9 or 9.8
1
1
1, 3
2, 3
1
Auto-Negotiation Complete bit (1.5)
is set.
1
99 of 165
Register
9. Bit 10.14 indicates the final MASTER/SLAVE
is set.
Datasheet
VSC8211