PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 11

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
1
1.1
1.2
1.2.1 PRIMARY BUS INTERFACE SIGNALS
SIGNAL DEFINITIONS
SIGNAL TYPES
SIGNALS
Signals that end with “#” are active LOW.
SIGNAL TYPE
I
O
P
TS
STS
OD
Name
P_AD[31:0]
P_CBE#[3:0]
P_PAR
P_FRAME#
P_IRDY#
Pin Number
125, 126, 127, 2, 5, 6,
7, 8, 9, 10, 12, 13, 25,
26, 27, 28, 30, 31, 32,
33, 35, 36, 37, 40, 41,
42, 43, 44
23
15
16
121, 122, 123, 124,
3, 14, 24, 34
DESCRIPTION
Input only
Output only
Power
Tri-state bi-directional
Sustained tri-state. Active LOW signal must be pulled HIGH for 1 cycle
when deasserting.
Open Drain
Type
STS
STS
TS
TS
TS
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Description
Primary Address / Data: Multiplexed address and data bus.
Address is indicated by P_FRAME# assertion. Write data is
stable and valid when P_IRDY# is asserted and read data is
stable and valid when P_TRDY# is asserted. Data is transferred
on rising clock edges when both P_IRDY# and P_TRDY# are
asserted. During bus idle, PI7C8140A drives P_AD to a valid
logic level when P_GNT# is asserted.
Primary Command/Byte Enables: Multiplexed command field
and byte enable field. During address phase, the initiator drives
the transaction type on these pins. After that, the initiator drives
the byte enables during data phases. During bus idle, PI7C8140A
drives P_CBE#[3:0] to a valid logic level when P_GNT# is
asserted.
Primary Parity. Parity is even across P_AD[31:0],
P_CBE#[3:0], and P_PAR (i.e. an even number of 1’s). P_PAR
is an input and is valid and stable one cycle after the address
phase (indicated by assertion of P_FRAME#) for address parity.
For write data phases, P_PAR is an input and is valid one clock
after P_IRDY# is asserted. For read data phase, P_PAR is an
output and is valid one clock after P_TRDY# is asserted. Signal
P_PAR is tri-stated one cycle after the P_AD lines are tri-stated.
During bus idle, PI7C8140A drives P_PAR to a valid logic level
when P_GNT# is asserted.
Primary FRAME (Active LOW). Driven by the initiator of a
transaction to indicate the beginning and duration of an access.
The de-assertion of P_FRAME# indicates the final data phase
requested by the initiator. Before being tri-stated, it is driven to
a de-asserted state for one cycle.
Primary IRDY (Active LOW). Driven by the initiator of a
transaction to indicate its ability to complete current data phase
on the primary side. Once asserted in a data phase, it is not de-
asserted until the end of the data phase. Before tri-stated, it is
driven to a de-asserted state for one cycle.
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A