PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 22

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
2.6.4 READ PREFETCH ADDRESS BOUNDARIES
2.6.5 DELAYED READ REQUESTS
The bridge imposes internal read address boundaries on read pre-fetched data. When a read transaction
reaches one of these aligned address boundaries, the bridge stops pre-fetched data, unless the target
signals a target disconnect before the read pre-fetched boundary is reached. When the bridge finishes
transferring this read data to the initiator, it returns a target disconnect with the last data transfer, unless
the initiator completes the transaction before all pre-fetched read data is delivered. Any leftover pre-
fetched data is discarded.
Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB address
boundary, or until the initiator de-asserts FRAME_L. Section 2.6.7 describes flow-through mode during
read operations.
Table 2-4 shows the read prefetch address boundaries for read transactions during non-flow-through
mode.
Table 2-4. Read Prefetch Address Boundaries
- does not matter if it is prefetchable or non-prefetchable
* don’t care
Table 2-5. Read Transaction Prefetching
See Section 3.3 for detailed information about prefetchable and non-prefetchable address spaces.
The bridge treats all read transactions as delayed read transactions, which means that the read request
from the initiator is posted into a delayed transaction queue. Read data from the target is placed in the
read data queue directed toward the initiator bus interface and is transferred to the initiator when the
initiator repeats the read transaction.
When the bridge accepts a delayed read request, it first samples the read address, read bus command,
and address parity. When IRDY# is asserted, the bridge then samples the byte enable bits for the first
data phase. This information is entered into the delayed transaction queue. The bridge terminates the
transaction by signaling a target retry to the initiator. Upon reception of the target retry, the initiator is
Type of Transaction
Configuration Read
I/O Read
Memory Read
Memory Read
Memory Read
Memory Read Line
Memory Read Line
Memory Read Multiple
Memory Read Multiple
Type of Transaction
I/O Read
Configuration Read
Memory Read
Memory Read Line
Memory Read Multiple
Address Space
-
-
Non-Prefetchable
Prefetchable
Prefetchable
-
-
-
-
Read Behavior
Prefetching never allowed
Prefetching never allowed
Downstream: Prefetching used if address is prefetchable space
Upstream: Prefetching used or programmable
Prefetching always used
Prefetching always used
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Cache
CLS = 1, 2, 4, 8, 16
(CLS)
*
*
*
CLS = 0 or 16
CLS = 1, 2, 4, 8, 16
CLS = 0 or 16
CLS = 1, 2, 4, 8, 16
CLS = 0 or 16
Line
Size
Prefetch Aligned Address Boundary
One DWORD (no prefetch)
One DWORD (no prefetch)
One DWORD (no prefetch)
16-DWORD aligned address boundary
Cache line address boundary
16-DWORD aligned address boundary
Cache line boundary
32-DWORD aligned address boundary
2X of cache line boundary
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A