PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 31

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
2.8.3.3 DELAYED READ TARGET TERMINATION RESPONSE
2.8.4 TARGET TERMINATION INITIATED BY PI7C8140A
2.8.4.1 TARGET RETRY
When the bridge initiates a delayed read transaction, the abnormal target responses can be passed back
to the initiator. Other target responses depend on how much data the initiator requests. Table 2-9 shows
the response to each type of target termination that occurs during a delayed read transaction.
The bridge repeats a delayed read transaction until one of the following conditions is met:
The bridge makes 2
Table 2-9. Response to Delayed Read Target Termination
After the bridge makes 2
bridge asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command register for
secondary bus) and the delayed-write-non-delivery bit is not set. The delayed-write-non-delivery bit is
bit 5 of P_SERR# event disable register (offset 64h). The bridge will report system error. See Section
5.4 for a description of system error conditions.
The bridge can return a target retry, target disconnect, or target abort to an initiator for reasons other
than detection of that condition at the target interface.
The bridge returns a target retry to the initiator when it cannot accept write data or return read data as a
result of internal conditions. The bridge returns a target retry to an initiator when any of the following
conditions is met:
For delayed write transactions:
Target Termination
Normal
Target Retry
Target Disconnect
Target Abort
Bridge completes at least one data transfer.
Bridge receives a master abort.
Bridge receives a target abort.
The transaction is being entered into the delayed transaction queue.
Transaction has already been entered into delayed transaction queue, but target response has not yet
Target response has been received but has not progressed to the head of the return queue.
The delayed transaction queue is full, and the transaction cannot be queued.
A transaction with the same address and command has been queued.
A locked sequence is being propagated across the bridge, and the write transaction is not a locked
The target bus is locked and the write transaction is a locked transaction.
been received.
transaction.
24
(default) read attempts resulting in a response of target retry.
Response
If prefetchable, target disconnect only if initiator requests more data than read from target. If
non-prefetchable, target disconnect on first data phase.
Re-initiate read transaction to target
If initiator requests more data than read from target, return target disconnect to initiator.
Return target abort to initiator. Set received target abort bit in the target interface status
register. Set signaled target abort bit in the initiator interface status register.
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(default) attempts of the same delayed read transaction on the target bus, the
Page 31 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A