PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 35

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
3.3
3.3.1 MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS
are forwarded downstream. Transactions above the 64KB I/O address boundary are forwarded as
defined by the address range defined by the I/O base and limit registers.
Accordingly, if the ISA enable bit is set, the bridge forwards upstream those I/O transactions addressing
the top 768 bytes of each aligned 1KB block within the first 64KB of I/O space. The master enable bit
in the command configuration register must also be set to enable upstream forwarding. All other I/O
transactions initiated on the secondary bus are forwarded upstream only if they fall outside the I/O
address range.
When the ISA enable bit is set, devices downstream of the bridge can have I/O space mapped into the
first 256 bytes of each 1KB chunk below the 64KB boundary, or anywhere in I/O space above the
64KB boundary.
MEMORY ADDRESS DECODING
The bridge has three mechanisms for defining memory address ranges for forwarding of memory
transactions:
This section describes the first two mechanisms. Section 3.4.1 describes VGA mode. To enable
downstream forwarding of memory transactions, the memory enable bit must be set in the command
register in configuration space. To enable upstream forwarding of memory transactions, the master-
enable bit must be set in the command register. The master-enable bit also allows upstream forwarding
of I/O transactions if it is set.
CAUTION
If any configuration state affecting memory transaction forwarding is changed by a configuration write
operation on the primary bus at the same time that memory transactions are ongoing on the secondary
bus, response to the secondary bus memory transactions is not predictable. Configure the memory-
mapped I/O base and limit address registers, prefetchable memory base and limit address registers,
and VGA mode bit before setting the memory enable and master enable bits, and change them
subsequently only when the primary and secondary PCI buses are idle.
Memory-mapped I/O is also referred to as non-prefetchable memory. Memory addresses that cannot
automatically be pre-fetched but that can be conditionally pre-fetched based on command type should
be mapped into this space. Read transactions to non-prefetchable space may exhibit side effects; this
space may have non-memory-like behavior. The bridge prefetches in this space only if the memory
read line or memory read multiple commands are used; transactions using the memory read command
are limited to a single data transfer.
The memory-mapped I/O base address and memory-mapped I/O limit address registers define an
address range that the bridge uses to determine when to forward memory commands. The bridge
forwards a memory transaction from the primary to the secondary interface if the transaction address
falls within the memory-mapped I/O address range. The bridge ignores memory transactions initiated
Memory-mapped I/O base and limit address registers
Prefetchable memory base and limit address registers
VGA mode
Page 35 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A