PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 53

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
9
10
10.1 PRIMARY INTERFACE RESET
PCI POWER MANAGEMENT
The bridge incorporates functionality that meets the requirements of the PCI Power Management
Specification, Revision 1.1. These features include:
Table 9-1 shows the states and related actions that the bridge performs during power management
transitions. (No other transactions are permitted.)
Table 9-1. Power Management Transitions
PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME# signals do not
pass through PCI-to-PCI bridges.
RESET
This chapter describes the primary interface, secondary interface, and chip reset mechanisms.
The bridge has a reset input, P_RST#. When P_RST# is asserted, the following events occur:
P_RST# asserting and de-asserting edges can be asynchronous to P_CLK and S_CLKOUT. The bridge
is not accessible during P_RST#. After P_RST# is de-asserted, the bridge remains inaccessible for 16
PCI clocks before the first configuration transaction can be accepted.
D0
D0
D0
D0
D3hot
D3hot
D3cold
Current Status
PCI Power Management registers using the Enhanced Capabilities Port (ECP) address mechanism
Support for D0, D3
Support for D0, D1, D2, D3
Support of the B2 secondary bus power state when in the D3
Bridge immediately tri-states all primary and secondary PCI interface signals.
Bridge performs a chip reset.
Registers that have default values are reset.
D3cold
D3hot
D2
D1
D0
D3cold
D0
Next State
hot
,
and D3
hot
cold
, and D3
Power has been removed from bridge. A power-up reset must be performed to
bring bridge to D0.
If enabled to do so by the BPCCE pin, bridge will disable the secondary clocks
and drive them LOW.
Unimplemented power state. bridge will ignore the write to the power state
bits (power state remains at D0).
Unimplemented power state. bridge will ignore the write to the power state
bits (power state remains at D0).
Bridge enables secondary clock outputs and performs an internal chip reset.
Signal S_RST# will not be asserted. All registers will be returned to the reset
values and buffers will be cleared.
Power has been removed from bridge. A power-up reset must be performed to
bring bridge to D0.
Power-up reset. Bridge performs the standard power-up reset functions as
described in Section 10.
power management states
Page 53 of 82
cold
power management states for devices behind the bridge
hot
Action
power management state
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A