PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 20

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
2.5.4 WRITE TRANSACTION BOUNDARIES
2.5.5 BUFFERING MULTIPLE WRITE TRANSACTIONS
2.5.6 FAST BACK-TO-BACK TRANSACTIONS
2.6
discards the delayed write completion from the delayed transaction completion queue. The bridge also
conditionally asserts P_SERR# (see Section 5.4).
The bridge imposes internal address boundaries when accepting write data. The aligned address
boundaries are used to prevent the bridge from continuing a transaction over a device address boundary
and to provide an upper limit on maximum latency. The bridge returns a target disconnect to the
initiator when it reaches the aligned address boundaries under conditions shown in Table 2-3.
Table 2-3. Write Transaction Disconnect Address Boundaries
Note 1. Memory write disconnect control bit is bit 1 of the chip control register at offset 44h in the configuration space.
The bridge continues to accept posted memory write transactions as long as space for at least one
DWORD of data in the posted write data buffer remains. If the posted write data buffer fills before the
initiator terminates the write transaction, the bridge returns a target disconnect to the initiator.
Delayed write transactions are posted as long as at least one open entry in the delayed transaction queue
exists. Therefore, several posted and delayed write transactions can exist in data buffers at the same
time. See Chapter 5 for information about how multiple posted and delayed write transactions are
ordered.
The bridge can recognize and post fast back-to-back write transactions. When the bridge cannot accept
the second transaction because of buffer space limitations, it returns a target retry to the initiator. The
fast back-to-back enable bit must be set in the command register for upstream write transactions, and in
the bridge control register for downstream write transactions.
READ TRANSACTIONS
Delayed read forwarding is used for all read transactions crossing the bridge. Delayed read transactions
are treated as either prefetchable or non-prefetchable. Table 2-5 shows the read behavior, prefetchable
or non-prefetchable, for each type of read operation.
Type of Transaction
Delayed Write
Posted Memory Write
Posted Memory Write
Posted Memory Write and
Invalidate
Posted Memory Write and
Invalidate
Condition
All
Memory write disconnect control bit = 0
Memory write disconnect control bit = 1
Cache line size ≠ 1, 2, 4, 8, 16
Cache line size = 1, 2, 4, 8, 16
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Aligned Address Boundary
Disconnects after one data transfer
4KB aligned address boundary
Disconnects at cache line boundary
4KB aligned address boundary
Cache line boundary if posted memory
write data FIFO does not have enough
space for the cache line
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A