PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 47

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
X = don’t care
Table 5-3 shows setting data parity detected bit in the primary interface’s status register. This bit is set
under the following conditions:
Table 5-3. Setting Primary Interface Master Data Parity Error Detected Bit
X = don’t care
Table 5-4 shows setting the data parity detected bit in the status register of secondary interface. This bit
is set under the following conditions:
Table 5-4. Setting Secondary Interface Master Data Parity Error Detected Bit
X= don’t care
Secondary
Detected
Error Bit
0
0
1
Primary
Parity Bit
0
0
1
0
0
0
1
0
0
0
1
0
Secondary
Detected
Detected Bit
0
1
0
0
0
1
0
0
0
1
0
0
Bridge must be a master on the primary bus.
The parity error response bit in the command register, corresponding to the primary interface, must
be set.
The P_PERR# signal is detected asserted or a parity error is detected on the primary bus.
The bridge must be a master on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary interface.
The S_PERR# signal is detected asserted or a parity error is detected on the secondary bus.
Parity
Parity
Data
Transaction Type
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Direction
Downstream
Upstream
Upstream
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
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Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Bus Where Error
Bus Where Error
Was Detected
Was Detected
Was Detected
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
x / x
x / x
x / x
x / x
x / x
1 / x
x / x
x / x
x / x
1 / x
x / x
x / x
x / x
1 / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
Primary/ Secondary Parity
Primary / Secondary Parity
Primary / Secondary Parity
Error Response Bits
Error Response Bits
Error Response Bits
PI7C8140A