PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 49

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
5.4
Table 5-7. Assertion of P_SERR# for Data Parity Errors
X = don’t care
2
3
SYSTEM ERROR (SERR#) REPORTING
The bridge uses the P_SERR# signal to report conditionally a number of system error conditions in
addition to the special case parity error conditions described in Section 5.2.3.
Whenever assertion of P_SERR# is discussed in this document, it is assumed that the following
conditions apply:
In compliance with the PCI-to-PCI Bridge Architecture Specification, the bridge asserts P_SERR#
when it detects the secondary SERR# input, S_SERR#, asserted and the SERR# forward enable bit is
set in the bridge control register. In addition, the bridge also sets the received system error bit in the
secondary status register.
The bridge also conditionally asserts P_SERR# for any of the following reasons:
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
P_SERR#
1 (de-asserted)
1
1
1
1
0
0
1
1
1
1
1
2
3
(asserted)
The bridge has detected P_PERR# asserted on an upstream posted write transaction or S_PERR#
asserted on a downstream posted write transaction.
The bridge did not detect the parity error as a target of the posted write transaction.
The parity error response bit on the command register and the parity error response bit on the
bridge control register must both be set.
The SERR# enable bit must be set in the command register.
For the bridge to assert P_SERR# for any reason, the SERR# enable bit must be set in the
command register.
Whenever the bridge asserts P_SERR#, the bridge must also set the signaled system error bit in the
status register.
Target abort detected during posted write transaction
Master abort detected during posted write transaction
Posted write data discarded after 2
Parity error reported on target bus during posted write transaction (see previous section)
Delayed write data discarded after 2
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
24
24
Page 49 of 82
(default) attempts to deliver (2
(default) attempts to deliver (2
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Was Detected
2-PORT PCI-TO-PCI BRIDGE
24
March 20, 2007 – Revision 1.01
24
target retries received)
x / x
x / x
x / x
x / x
x / x
1 / 1
1 / 1
x / x
x / x
x / x
x / x
x / x
target retries received)
Primary / Secondary Parity
Error Response Bits
PI7C8140A