PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 70

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
13.2.32 ARBITER CONTROL REGISTER – OFFSET 44h
13.2.33 EXTENDED CHIP CONTROL REGISTER – OFFSET 48h
Bit
19:16
24:20
25
31:26
Bit
0
1
2
3
Function
Arbiter Control
Reserved
Priority of
Secondary
Interface
Reserved
Function
Memory Read
Flow Through
Enable
Park
Downstream
Dynamic
Prefetching
Control
Upstream
Dynamic
Prefetching
Control
Type
RW
RO
RW
RO
Type
RW
RW
RW
RW
Reserved. Returns 0 when read. Reset to 0.
Reserved. Returns 0 when read. Reset to 0.
Description
Each bit controls whether a secondary bus master is assigned to the high priority
group or the low priority group.
Bits [19:16] correspond to request inputs S_REQ#[3:0]
0: low priority
1: high priority
Reset to 0
Controls whether the secondary interface of the bridge is in the high priority
group or the low priority group.
0: low priority
1: high priority
Reset to 1
Description
0: Disable flow through during a memory read transaction
1: Enable flow through during a memory read transaction
Reset to 0
Controls bus arbiter’s park function
0: Park to last master
1: Park to the bridge – secondary port
Reset to 0
Controls the downstream (P to S) memory read line and memory read multiple
prefetching dynamic control
0: Enable the downstream memory read line and memory read multiple
prefetching dynamic control
1: Disable the downstream memory read line and memory read multiple
prefetching dynamic control
Reset to 0
Controls the upstream (S to P) memory read line and memory read multiple
prefetching dynamic control
0: Enable the upstream memory read line and memory read multiple prefetching
dynamic control
1: Disable the upstream memory read line and memory read multiple prefetching
dynamic control
Reset to 0
Page 70 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A