PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 28

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
2.8.1 MASTER TERMINATION INITIATED BY PI7C8140A
The target can terminate transactions with one of the following types of termination:
The bridge, as an initiator, uses normal termination if DEVSEL# is returned by target within five clock
cycles of the bridge’s assertion of FRAME# on the target bus. As an initiator, the bridge terminates a
transaction when the following conditions are met:
If the bridge is delivering posted write data when it terminates the transaction because the master
latency timer expires, it initiates another transaction to deliver the remaining write data. The address of
the transaction is updated to reflect the address of the current DWORD to be delivered.
Normal termination
Normal termination occurs when the initiator de-asserts FRAME# at the beginning of the last data
phase, and de-asserts IRDY# at the end of the last data phase in conjunction with either TRDY# or
STOP# assertion from the target.
Master abort
A master abort occurs when no target response is detected. When the initiator does not detect a
DEVSEL# from the target within five clock cycles after asserting FRAME#, the initiator terminates
the transaction with a master abort. If FRAME# is still asserted, the initiator de-asserts FRAME#
on the next cycle, and then de-asserts IRDY# on the following cycle. IRDY# must be asserted in
the same cycle in which FRAME# de-asserts. If FRAME# is already de-asserted, IRDY# can be
de-asserted on the next clock cycle following detection of the master abort condition.
Normal termination
TRDY# and DEVSEL# asserted in conjunction with FRAME# de-asserted and IRDY# asserted.
Target retry
STOP# and DEVSEL# asserted with TRDY# de-asserted during the first data phase. No data
transfers occur during the transaction. This transaction must be repeated.
Target disconnect with data transfer
STOP#, DEVSEL# and TRDY# asserted. It signals that this is the last data transfer of the
transaction.
Target disconnect without data transfer
STOP# and DEVSEL# asserted with TRDY# de-asserted after previous data transfers have been
made. Indicates that no more data transfers will be made during this transaction.
Target abort
STOP# asserted with DEVSEL# and TRDY# de-asserted. Indicates that target will never be able to
complete this transaction. DEVSEL# must be asserted for at least one cycle during the transaction
before the target abort is signaled.
During a delayed write transaction, a single DWORD is delivered.
During a non-prefetchable read transaction, a single DWORD is transferred from the target.
During a prefetchable read transaction, a pre-fetch boundary is reached.
For a posted write transaction, all write data for the transaction is transferred from data buffers to
the target.
For burst transfer, with the exception of “Memory Write and Invalidate” transactions, the master
latency timer expires and the bridge’s bus grant is de-asserted.
The target terminates the transaction with a retry, disconnect, or target abort.
Page 28 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A