PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 69

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
Bit
1
3:2
4
7:5
8
9
11:10
12
15:13
Function
Memory Write
Disconnect
Control
Reserved
Secondary Bus
Prefetch
Disable
Reserved
Chip Reset
Test Mode 1
Test Mode 2
Test Mode 3
Reserved
Type
RW
RO
RW
RO
RWR
RW
RW
RW
RO
Description
Controls when the bridge (as a target) disconnects memory write transactions.
0: memory write disconnects at 4KB aligned address boundary
1: memory write disconnects at cache line aligned address boundary
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
Controls the bridge’s ability to prefetch during upstream memory read
transactions
0: Bridge prefetches and does not forward byte enable bits during upstream
memory read transactions.
1: Bridge requests only 1 DWORD from the target and forwards read byte enable
bits during upstream memory reads.
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Controls the chip and secondary bus reset.
0: Bridge is ready for operation
1: Causes bridge to perform a chip reset. Data buffers, configuration registers, and
both primary and secondary are reset to their initial states. Bridge clears this bit
once chip reset is complete. Bridge can then be reconfigured.
Controls the ability to test bridge’s behavior
0: minimum of 8 free space in data FIFO to accept memory burst writes
1: minimum of 1 free space in data FIFO to accept memory burst writes
Reset to 0
Controls the ability to test bridge’s behavior
00: enable out of order transactions between all 4 DTR requests
01: accept 3 DTR requests at a time and they may be out of order
10: only the 2 DTR requests at the top of the 2 FIFO’s may be out of order
11: no out of order transactions supported between DTR requests
Reset to 00
Controls the ability to test bridge’s behavior
0: 4 memory write transactions can be accepted at a time
1: 2 memory write transactions can be accepted at a time
Reset to 0
Reserved. Returns 000 when read. Reset to 000.
Page 69 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A