PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 46

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
5.3
Assertion of P_SERR# is used to signal the parity error condition when the initiator does not know that
the error occurred. Because the data has already been delivered with no errors, there is no other way to
signal this information back to the initiator. If the parity error has forwarded from the initiating bus to
the target bus, P_SERR# will not be asserted.
DATA PARITY ERROR REPORTING SUMMARY
In the previous sections, the responses of the bridge to data parity errors are presented according to the
type of transaction in progress. This section organizes the responses of the bridge to data parity errors
according to the status bits that the bridge sets and the signals that it asserts. Table 5-1 shows setting
the detected parity error bit in the status register, corresponding to the primary interface. This bit is set
when the bridge detects a parity error on the primary interface.
Table 5-1. Setting the Primary Interface Detected Parity Error Bit
X = don’t care
Table 5-2 shows setting the detected parity error bit in the secondary status register, corresponding to
the secondary interface. This bit is set when the bridge detects a parity error on the secondary interface.
Table 5-2. Setting Secondary Interface Detected Parity Error Bit
Primary Detected
Parity Error Bit
0
0
1
0
1
0
0
0
1
0
0
0
Secondary
Detected
Error Bit
0
1
0
0
0
0
0
1
0
Parity
The SERR# enable bit is set in the command register.
The parity error response bit is set in the bridge control register of the secondary interface.
The parity error response bit is set in the command register of the primary interface.
Bridge has not detected the parity error on the secondary (initiator) bus, which the parity
error is not forwarded from the secondary bus to the primary bus.
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
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Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Bus Where Error
Bus Where Error
Was Detected
Was Detected
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
Primary/ Secondary Parity
Primary/ Secondary Parity
Error Response Bits
Error Response Bits
PI7C8140A