PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 56

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
11.2 SECONDARY INTERFACE
12
12.1 BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES
BRIDGE BEHAVIOR
A PCI cycle is initiated by asserting the FRAME# signal. In a bridge, there are a number of
possibilities. Those possibilities are summarized in the table below:
P_CBE [3:0]
1110
1111
S_CBE[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Initiator
Master on Primary
Command
Memory Read Line
Memory Write and
Invalidate
Command
Interrupt
Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read
Multiple
Dual Address Cycle
Memory Read Line
Memory Write and
Invalidate
Target
Target on Primary
Action
Same as Memory Read
Same as Memory Read
Action
Ignore
Do not claim. Ignore.
Same as Primary Interface
Same as I/O Read.
-----
-----
Same as Primary Interface
Same as Memory Read.
-----
-----
Ignore
I. Type 0 Configuration Write: Ignore
II. Type 1 Configuration Write (not special cycle request):Ignore
III. Configuration Write as Special Cycle Request (device = 1Fh,
function = 7h):
1. If the target bus is the bridge’s primary bus: claim and pass through as
a Special Cycle
2. If the target bus is neither the primary bus nor is it in range of buses
defined by the bridge’s secondary and subordinate bus registers: claim
and pass through unchanged as a Type 1 Configuration Write.
3. If the target bus is not the bridge’s primary bus, but is in range of buses
defined by the bridge’s secondary and subordinate bus registers: ignore.
Same as Memory Read
Supported
Same as Memory Read
Same as Memory Read
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Response
Bridge does not respond. It detects this situation by
decoding the address as well as monitoring the
P_DEVSEL# for other fast and medium devices on the
Primary Port.
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A