PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 67

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
13.2.28 BRIDGE CONTROL REGISTER – OFFSET 3Ch
Bit
16
17
18
19
20
21
22
23
Function
Parity Error
Response
S_SERR#
enable
ISA enable
VGA enable
Reserved
Master Abort
Mode
Secondary
Interface Reset
Fast Back-to-
Back Enable
Type
RW
RW
RW
RW
R/O
RW
RW
RW
Reserved. Returns 0 when read. Reset to 0
Description
0: ignore address and data parity errors on the secondary interface
1: enable parity error reporting and detection on the secondary interface
Reset to 0
0: disable the forwarding of S_SERR# to primary interface
1: enable the forwarding of S_SERR# to primary interface
Reset to 0
Modifies the bridge’s response to ISA I/O addresses, applying only to those
addresses falling within the I/O base and limit address registers and within the
first 64KB of PCI I/O space.
0: forward all I/O addresses in the range defined by the I/O base and I/O limit
registers
1: blocks forwarding of ISA I/O addresses in the range defined by the I/O base
and I/O limit registers that are in the first 64KB of I/O space that address the last
768 bytes in each 1KB block. Secondary I/O transactions are forwarded upstream
if the address falls within the last 768 bytes in each 1KB block
Reset to 0
0: does not forward VGA compatible memory and I/O addresses from primary to
secondary
1: forward VGA compatible memory and I/O addresses from primary to
secondary regardless of other settings
Reset to 0
0: does not report master aborts (returns FFFF_FFFFh on reads and discards data
on writes)
1: reports master aborts by signaling target abort if possible or by the assertion of
P_SERR# if enabled
Reset to 0
0: does not force the assertion of S_RESET# pin
1: forces the assertion of S_RESET#
Reset to 0
Controls bridge’s ability to generate fast back-to-back transactions to different
devices on the secondary interface.
0: does not generate fast back-to-back transactions on the secondary
1: enables fast back-to-back transaction generation on the secondary
Reset to 0
Page 67 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A